From 006ccf510a1fa517950c890de2c7c4dbef0d752e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 9 Mar 2020 20:37:58 +0100
Subject: testsuite/synth: add a test for previous commit.

---
 testsuite/synth/arr02/arr02.vhdl    | 38 ++++++++++++++++++++++++++++
 testsuite/synth/arr02/tb_arr02.vhdl | 49 +++++++++++++++++++++++++++++++++++++
 testsuite/synth/arr02/testsuite.sh  |  2 +-
 3 files changed, 88 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/arr02/arr02.vhdl
 create mode 100644 testsuite/synth/arr02/tb_arr02.vhdl

diff --git a/testsuite/synth/arr02/arr02.vhdl b/testsuite/synth/arr02/arr02.vhdl
new file mode 100644
index 000000000..2f0890ee2
--- /dev/null
+++ b/testsuite/synth/arr02/arr02.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity arr02 is
+  port (
+    a : std_logic_vector (31 downto 0);
+    sel : natural range 0 to 3;
+    clk : std_logic;
+    res : out std_logic_vector (3 downto 0));
+end arr02;
+
+architecture behav of arr02 is
+  type t_mem is array (0 to 3) of std_logic_vector (7 downto 0);
+  type t_stage is record
+    sel : natural range 0 to 3;
+    val : t_mem;
+  end record;
+
+  signal s : t_stage;
+begin
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      s.sel <= sel;
+      s.val <= (a (31 downto 24),
+                a (23 downto 16),
+                a (15 downto 8),
+                a (7 downto 0));
+    end if;
+  end process;
+
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      res <= s.val (s.sel)(3 downto 0);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/tb_arr02.vhdl b/testsuite/synth/arr02/tb_arr02.vhdl
new file mode 100644
index 000000000..2c9c58e6d
--- /dev/null
+++ b/testsuite/synth/arr02/tb_arr02.vhdl
@@ -0,0 +1,49 @@
+entity tb_arr02 is
+end tb_arr02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_arr02 is
+  signal a : std_logic_vector (31 downto 0);
+  signal sel : natural range 0 to 3;
+  signal clk : std_logic;
+  signal res : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.arr02
+    port map (a, sel, clk, res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    a <= x"a1b2c3d4";
+    sel <= 0;
+    pulse;
+    pulse;
+    assert res = x"1" severity failure;
+
+    sel <= 1;
+    pulse;
+    assert res = x"1" severity failure;
+
+    sel <= 2;
+    pulse;
+    assert res = x"2" severity failure;
+
+    sel <= 3;
+    pulse;
+    assert res = x"3" severity failure;
+
+    sel <= 0;
+    pulse;
+    assert res = x"4" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/testsuite.sh b/testsuite/synth/arr02/testsuite.sh
index c3a077cf9..441d8285d 100755
--- a/testsuite/synth/arr02/testsuite.sh
+++ b/testsuite/synth/arr02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in arr01; do
+for t in arr01 arr02; do
     synth_tb $t
 done
 
-- 
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