iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl-sem_assocs: recurse for individual associations.	Tristan Gingold	2020-02-17	1	-23/+64
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*	synth: allow constant condition for if-generate statement.	Tristan Gingold	2020-02-17	1	-0/+1
\| \| \| \|	For #1076
*	synth: add mdff.	Tristan Gingold	2020-02-17	4	-12/+88
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*	netlists-inference: remove useless code.	Tristan Gingold	2020-02-16	1	-10/+0
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*	synthesis: rework memory inference.	Tristan Gingold	2020-02-16	3	-32/+101
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*	synth: handle component with ports in different order.	Tristan Gingold	2020-02-13	3	-45/+46
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*	vhdl-parse: improve recovery for incorrect end identifier.	Tristan Gingold	2020-02-13	1	-8/+27
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*	files_maps-editor: fix incorrect assertion.	Tristan Gingold	2020-02-13	1	-1/+1
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*	vhdl-sem_expr: avoid a crash on incorrect qualified expr.	Tristan Gingold	2020-02-13	1	-0/+6
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*	synth-static_oper: handle more division operands. Fix #1134	Tristan Gingold	2020-02-12	1	-1/+2
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*	synth: handle null vector for vec-vec concat. Fix #1133	Tristan Gingold	2020-02-11	2	-6/+12
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*	synth-oper: handle add for (natural, unsigned). Fix #1132	Tristan Gingold	2020-02-11	1	-0/+15
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*	netlists-memories: handle split memories. Fix #1127	Tristan Gingold	2020-02-11	1	-8/+18
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*	translate: refine condition. Fix #1125	Tristan Gingold	2020-02-11	1	-1/+1
\| \| \| \|	For the check of matching direction in slices.
*	synth-static_oper: handle xor.	Tristan Gingold	2020-02-10	1	-0/+11
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*	synth-expr: implement value and val attributes. Fix #1130	Tristan Gingold	2020-02-10	1	-1/+39
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*	grt: split grt-errors, disp current process.	Tristan Gingold	2020-02-10	18	-104/+183
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*	synth: remove remaining clock edge gates after memories.	Tristan Gingold	2020-02-10	2	-0/+26
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*	netlists-memories: cleanup.	Tristan Gingold	2020-02-10	1	-319/+1
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*	synth: rework (again) memory inference.	Tristan Gingold	2020-02-10	8	-80/+312
\| \| \| \| \| \|	Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference.
*	synth-inference: minor refactoring.	Tristan Gingold	2020-02-06	1	-24/+7
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*	synth-decls: set a default value to non-assigned signals. Fix #1107	Tristan Gingold	2020-02-05	1	-1/+3
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*	netlists-disp_vhdl: handle 1-bit const_x. For #1107	Tristan Gingold	2020-02-05	1	-3/+9
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*	vhdl-sem_names: improve error location.	Tristan Gingold	2020-02-04	1	-1/+1
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*	vhdl-sem: improve error location for unknown entity.	Tristan Gingold	2020-02-04	1	-1/+1
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*	files_map: extract debug_source_file.	Tristan Gingold	2020-02-04	1	-40/+43
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*	files_map-editor: fix file_length when moving gap at end.	Tristan Gingold	2020-02-04	1	-1/+4
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*	files_map-editor: add more checks.	Tristan Gingold	2020-02-04	1	-0/+9
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*	vhdl-sem_expr: avoid a crash on invalid attribute name.	Tristan Gingold	2020-02-04	1	-1/+1
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*	vhdl-scanner: improve error message for empty quote.	Tristan Gingold	2020-02-04	1	-0/+6
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*	testsuite/gna: add a test for previous commit.	Tristan Gingold	2020-02-04	1	-0/+4
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*	vhdl-sem_utils: handle non-object interface for	Tristan Gingold	2020-02-04	1	-4/+6
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*	vhdl-sem_expr: avoid a crash on invalid input.	Tristan Gingold	2020-02-04	1	-0/+5
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*	configuration: allow hex-string for generic override. Fix #1117	Tristan Gingold	2020-02-02	1	-17/+86
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*	trans-chap8: handle vector in aggregate target for variable assignments.	Tristan Gingold	2020-02-02	1	-23/+47
\| \| \| \|	Fix #1120
*	vhdl-sem_assocs: check conversion functions have only one parameter.	Tristan Gingold	2020-02-02	1	-0/+8
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*	vhdl-sem_assocs: check that interface of function conv is a constant.	Tristan Gingold	2020-02-01	1	-1/+14
\| \| \| \|	Fix #1123
*	vhdl-sem_assocs: minor rework.	Tristan Gingold	2020-02-01	1	-32/+32
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*	ghdllocal: remove unused use clause.	Tristan Gingold	2020-02-01	1	-1/+0
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*	ghdllocal: add command --elab-order	Tristan Gingold	2020-02-01	2	-1/+72
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*	synth-inference: use the mux output to detect end of walk. Fix #1122	Tristan Gingold	2020-02-01	1	-1/+8
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*	synth-oper: handle std_match for slv. Close #1121	Tristan Gingold	2020-01-31	1	-1/+2
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*	trans-chap8: optimize assignment for non-overlapping targets.	Tristan Gingold	2020-01-31	1	-11/+108
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*	netlists-expands: also handle ror.	Tristan Gingold	2020-01-30	1	-7/+24
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*	synth: handle some rotation and shifts. Fix #1077	Tristan Gingold	2020-01-30	7	-1/+203
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*	ghdlcomp: renaming; allow files in any order for --synth.	Tristan Gingold	2020-01-30	4	-9/+15
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*	translate: add Convert_Array_Base. For #1038	Tristan Gingold	2020-01-27	3	-8/+29
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*	netlists-disp_vhdl: minor rework.	Tristan Gingold	2020-01-26	1	-2/+2
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*	synth: convert subtype on return. Fix #1116	Tristan Gingold	2020-01-26	1	-1/+1
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*	synth: avoid crash on incorrect slice direction. For #1116	Tristan Gingold	2020-01-26	2	-1/+10
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