aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
|
* vhdl-parse: support for-generate in vunits. Fix #1850Tristan Gingold2021-08-271-2/+10
|
* synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
| | | | For ghdl/ghdl-yosys-plugin#154
* std_names: add name keep.Tristan Gingold2021-08-272-1/+3
|
* netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
|
* ghdlsynth.adb: fix a typoTristan Gingold2021-08-261-1/+1
|
* PSL: handle inf in star repeat sequence. Fix #1832Tristan Gingold2021-08-269-11/+44
|
* vhdl-evaluation: check integer evaluations fit in base type. Fix #1834Tristan Gingold2021-08-262-11/+37
|
* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-255-20/+34
|
* ortho/gcc: adjust and propagate to all gcc versions the change for #1845Tristan Gingold2021-08-256-1/+81
|
* vhdl-sem_types.adb: refine conditions for resolution functions.Tristan Gingold2021-08-251-3/+7
| | | | | | | Do not consider that functions with unbounded elements can be a resolution function. For #1844
* ghdldrv: handle auxbase option in ortho/gcc. Fix #1845Tristan Gingold2021-08-242-10/+16
| | | | | Remove additional option in ghdldrv.adb, automatically set aux_base_name in ortho-lang-9.c
* vhdl-parse.adb: improve error recovery. For #1837Tristan Gingold2021-08-241-0/+2
|
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-2422-463/+198
|
* vhdl-sem_specs: avoid ownership issue on default map aspect.Tristan Gingold2021-08-241-1/+4
|
* Rework inertial associations.Tristan Gingold2021-08-238-46/+228
| | | | | Fix #1625 Fix #1672
* trans-chap3: handle (ignore) use clauses in protected types. Fix #1833Tristan Gingold2021-08-141-1/+2
|
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-0617-392/+482
|
* trans-chap7: handle strings in static array. Fix #1637Tristan Gingold2021-08-061-2/+2
|
* vhdl-sem_expr.adb: check matching subtype of array aggregate elements.Tristan Gingold2021-08-061-31/+67
| | | | | When the subtype of the aggregate is not known by the context. Fix #1723
* trans-chap3: do not create same range_var for enumeration subtype.Tristan Gingold2021-08-061-27/+41
| | | | | | As there is not ranges for enumerated type, a range_var was always created for subtypes of enumerated types even if they had the same range. Create the range_var for bool types.
* vhdl: adjust ownership of agrgegate element subtypes. Fix #1419Tristan Gingold2021-08-052-14/+31
| | | | | Disable transfer of array aggregate element subtype ownership, but create the info of aggregate element subtype.
* vhdl-sem_expr: add commentsTristan Gingold2021-08-041-0/+6
|
* vhdl-sem_expr: check subtype constraint of record aggregate elements.Tristan Gingold2021-08-041-1/+2
| | | | For #1419
* vhdl-disp_tree: disp integer literal valueTristan Gingold2021-08-041-15/+27
|
* vhdl-sem_expr.adb: build element subtype for aggregate when possible.Tristan Gingold2021-08-033-13/+164
| | | | | | | | In case of array aggregate whose element subtype is not bounded, extract it from the aggregate elements. Fix #1055 Fix #1455
* ghdldrv.adb: use cc (instead of gcc) as linker driver. Fix #1629Tristan Gingold2021-08-011-1/+1
|
* vhdl-parse: use if_generate_else_clause for elsif clauses. Fix #1824Tristan Gingold2021-07-291-1/+1
|
* vhdl-sem_expr: analyze choices before expressions in array aggregate.Tristan Gingold2021-07-281-22/+39
| | | | | Avoid considering expression to be possibly of the type of the aggregate if the choice is an expression.
* vhdl: move check on instantiation name from sem to parse.Tristan Gingold2021-07-282-1/+4
| | | | Fix #1823
* ghdldrv.adb: factorize code (for #1817)Tristan Gingold2021-07-231-68/+57
|
* ghdldrv.adb: pass option -auxbase to ghdl1. For #1817Tristan Gingold2021-07-231-1/+14
|
* vhdl-sem_stmts.adb: avoid a crash when forced analysis.Tristan Gingold2021-07-231-0/+4
|
* vhdl-utils(free_recursive): only free the name (not the entity)Tristan Gingold2021-07-221-1/+1
| | | | Fix #1820
* oread: add support for debug line declTristan Gingold2021-07-201-0/+7
|
* vhdl-sem_assocs: improve handling of generic typesTristan Gingold2021-07-191-17/+21
|
* trans-chap9: set line number for gcc. Fix #1817Tristan Gingold2021-07-191-2/+5
|
* vhdl-evaluation: handle element attribute. Fix #1818Tristan Gingold2021-07-171-1/+2
|
* vhdl-sem_stmts.adb: avoid a crash on invalid expressionTristan Gingold2021-07-051-1/+3
|
* vhdl-sem_scopes.adb: consider operators for interface chainTristan Gingold2021-07-051-1/+2
| | | | | | A type interface also implicitly declares equality and inequality operators for the type. Adjust Add_Declaration_From_Interface_Chain so that these operators are visible
* ghdllocal.adb: do not set Exec_Prefix if already set (by libghdl)Tristan Gingold2021-07-051-1/+4
|
* adjust previous commit (no identifier in Psl_Default_Clock)Tristan Gingold2021-07-014-3/+5
|
* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-305-107/+116
|
* vhdl: handle mod/rem for physical. Fix #1810Tristan Gingold2021-06-304-1/+23
|
* synth: minor renaming in netlists-memoriesTristan Gingold2021-06-303-10/+11
|
* src/ortho: adjust constructor for codacy warning.Tristan Gingold2021-06-301-1/+1
| | | | Not sure how legitimate it is.
* vhdl-nodes: do not reset free hooks on initializationTristan Gingold2021-06-263-2/+2
|
* synth-vhdl_context.adb(Is_Full): consider fractional words.Tristan Gingold2021-06-231-2/+16
|
* vhdl/Makefile: use python3 by defaultTristan Gingold2021-06-221-1/+1
|
* synth-vhdl_stmts: add location on AddidxTristan Gingold2021-06-211-0/+2
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 14:22:45 +0000