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| * Broken indentation.cderrien2022-05-171-5/+5
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| * Add the -Wall flag.cderrien2022-05-161-0/+9
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* | vhdl-nodes: remove unused fields for procedure declarationsTristan Gingold2022-05-172-219/+212
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* | vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-177-214/+264
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* | synth-vhdl_stmts: add a commentTristan Gingold2022-05-171-0/+2
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* | synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062Tristan Gingold2022-05-171-0/+1
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* | vhdl-canon: refactoring.Tristan Gingold2022-05-162-31/+87
|/ | | | Export procedures to extract sensitivity from concurrent statements
* vhdl-sem_specs: use by_name assoc for port default associationTristan Gingold2022-05-161-1/+5
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* ghdlcomp(common_compile_elab): add allow_undef_generic parameterTristan Gingold2022-05-164-4/+8
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* elab-vhdl_debug(disp_instance_path): can also display componentsTristan Gingold2022-05-162-7/+23
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* elab-vhdl_debug: factorize code, make Put_Dir publicTristan Gingold2022-05-162-12/+6
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* elab-vhdl_values: rename signal_index to signal_index_typeTristan Gingold2022-05-153-5/+5
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* grt-readline_none.adb: do not use getline(3)Tristan Gingold2022-05-151-19/+24
| | | | Not available on windows.
* elab-vhdl_values-debug: add disp_type_shortTristan Gingold2022-05-152-8/+58
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* elab-vhdl_debug: improve info signalsTristan Gingold2022-05-151-20/+19
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* elab-debugger: add append_info_menu, to_numTristan Gingold2022-05-152-5/+50
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* trans_analyzes: add support for all processesTristan Gingold2022-05-151-85/+116
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* elab-vhdl_debug(disp_instance_path): show top-level unitTristan Gingold2022-05-151-13/+5
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* elab-debugger: add append_menu_commandTristan Gingold2022-05-152-7/+29
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* synth: elab-debugger__on.adb is now elab-debugger.adbTristan Gingold2022-05-152-975/+929
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* configure: generate grt-readline.adsTristan Gingold2022-05-151-2/+0
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* grt: add grt-readline_gnu and grt-readline_noneTristan Gingold2022-05-155-14/+105
| | | | grt-readline is now a renaming of grt-readline_gnut
* grt: simplifies grt-readline, adjust casingTristan Gingold2022-05-155-17/+13
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* elab-vhdl_stmts: change parent of generate_body for for-generateTristan Gingold2022-05-141-1/+1
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* ghdlsimul: add and improve debuggerTristan Gingold2022-05-146-26/+471
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* vhdl-errors(disp_node): change message for generate bodyTristan Gingold2022-05-141-1/+1
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* elab-vhdl_context: add get_instance_parentTristan Gingold2022-05-142-0/+10
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* fix: avoid "pragma Unreferenced given" warnings with GCC 12Xiretza2022-05-143-3/+3
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* fix: avoid "unnecessary with of ancestor [-gnatwr]" with GCC 12Xiretza2022-05-144-5/+1
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* synth: implement file_open with statusTristan Gingold2022-05-123-0/+69
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* vhdl-canon: export extract_waveform_sensitivityTristan Gingold2022-05-121-2/+5
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* trans_analyzes.adb: reindentTristan Gingold2022-05-121-3/+2
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* synth-vhdl_stmts: export synth_targetTristan Gingold2022-05-122-35/+39
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* synth-vhdl_expr: add an hook to get the value of a signalTristan Gingold2022-05-122-0/+9
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* elab-vhdl_debug: also disp declarations in instancesTristan Gingold2022-05-121-4/+1
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* elab-memtype.adb: identationTristan Gingold2022-05-121-1/+1
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* ghdlsimul: add option -t to trace statementsTristan Gingold2022-05-121-0/+2
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* ghdllocal.adb: move pragma suppress. Fix #2056Tristan Gingold2022-05-121-1/+1
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* ghdlsimul: now based on synth elabTristan Gingold2022-05-112-101/+118
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* synth: handle text file writeTristan Gingold2022-05-113-0/+93
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* synth: add a flag to force creation of variablesTristan Gingold2022-05-115-9/+21
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* ghdlsynth.adb: remove -E experimental commandTristan Gingold2022-05-101-145/+42
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* synth: add current_stmt, minor reworkTristan Gingold2022-05-094-61/+99
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* synth-vhdl_insts: handle interfaces of type interface type. Fix #2053Tristan Gingold2022-05-071-1/+12
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* vhdl: consider fully static record aggregates. Fix #2051Tristan Gingold2022-05-074-26/+83
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* ortho/debug: handle aggregates of record-subtypeTristan Gingold2022-05-073-7/+25
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* elab-vhdl_context: introduce signal_indexTristan Gingold2022-05-063-3/+12
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* vhdl-sem.adb(are_trees_equal): handle selected element. Fix #2050Tristan Gingold2022-05-061-0/+4
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* vhdl-sem_names: second fix for #2048Tristan Gingold2022-05-031-1/+2
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* synth-vhdl_context: resize table before access. Fix #2049Tristan Gingold2022-05-021-6/+14
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