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* synth: handle static calls to signed numeric_std + -. Fix #1313Tristan Gingold2020-05-163-3/+119
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* synth: handle functional call to numeric_std binary operators. For #1313Tristan Gingold2020-05-162-25/+35
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* synth: handle inout ports with default values. For #1312Tristan Gingold2020-05-162-2/+7
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* synth-static_oper: handle eq_sgn_int comparision. For #1310Tristan Gingold2020-05-151-0/+56
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* trans-chap3: factorize code.Tristan Gingold2020-05-151-11/+1
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* synth: handle non-text file (add signatures).Tristan Gingold2020-05-156-10/+90
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* vhdl-utils: factorize Get_File_Signature.Tristan Gingold2020-05-154-134/+113
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* synth: handle initialized inout port. For #1312Tristan Gingold2020-05-155-39/+72
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* synth-flags: consider severity error as an error.Tristan Gingold2020-05-151-1/+1
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* synth-static_oper: handle more comparisons. Fix #1310Tristan Gingold2020-05-151-0/+41
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* synth: handle null array comparison. Fix #1311Tristan Gingold2020-05-153-11/+45
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* synth-stmts: ignore choices with L/H/W/X/Z/-/U values.Tristan Gingold2020-05-151-6/+86
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* synth-aggr: create constrained record type if needed.Tristan Gingold2020-05-142-8/+28
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* synth-stmts: factorize code for assertion errors, use a level.Tristan Gingold2020-05-142-33/+27
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* grt: move severity levels from errors to grt.severity.Tristan Gingold2020-05-146-8/+40
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* synth-values: tentatively try to fix warnings. For #1308Tristan Gingold2020-05-131-8/+12
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* synth-objtypes: tentatively try to fix warnings. For #1308Tristan Gingold2020-05-131-32/+48
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* vhdl-configuration: handle overrides of slv. Fix #1298Tristan Gingold2020-05-131-1/+15
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* trans-chap7: add a comment.Tristan Gingold2020-05-131-0/+3
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* synth-objtypes: use Address to avoid compiler warnings. For #1308.Tristan Gingold2020-05-131-23/+22
| | | | | Use intermediate type Address to convert between Memory_Ptr and scalar types, as Address has no alignment.
* synth: handle any constant as edge value. Fix #1302Tristan Gingold2020-05-131-27/+37
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* trans-chap5: handle record subtypes in port association.Tristan Gingold2020-05-131-13/+22
| | | | Part of #1300
* trans-chap7: Translate_Equality: also convert to base type for records.Tristan Gingold2020-05-133-26/+51
| | | | For #1300
* vhdl: translate_record_subtype: inherit from parent typeTristan Gingold2020-05-121-18/+24
| | | | (instead of base type). For #1300
* Adding some comments to the RTI processing. (#1304)Ben Reynwar2020-05-123-15/+73
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* Constants in vpi (#1297)Ben Reynwar2020-05-104-13/+47
| | | | | | | | | | | | | | | | | * Adding some very basic vpi tests. * Modify test so that's it's checking VPI access to constants. * Provide VPI to access constants. * Add vpi tests to testsuite. * Fix bug to allow getting values of generic/constant boolean and std_logic. * Fix stupid copying mistake in last commit. * Formatting and trying to get tests working on windows. * Fixing comment and removing redundant VhpiConstantDeclK
* synth_stmts: handle ranges in case. Fix ghdl/ghdl-yosys-plugin#104Tristan Gingold2020-05-091-9/+53
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* synth-stmts: refactoring for synth_choice.Tristan Gingold2020-05-091-85/+84
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* synth: correctly quote nets name in error messages.Tristan Gingold2020-05-094-10/+23
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* synth-stmts: use pmux to implement case statements.Tristan Gingold2020-05-092-130/+134
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* netlists-builders: add Build_Pmux.Tristan Gingold2020-05-094-1/+67
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* vhdl-sem_psl: handle next_event_a and next_event_e. Fix #1292Tristan Gingold2020-05-091-0/+5
| | | | From T. Meissner.
* netlists-gates: reserve pmux and latch.Tristan Gingold2020-05-092-93/+104
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* Add handling of N_Next_E in PSL semantic passtmeissner2020-05-081-1/+1
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* synth: handle vhdl-08 ports. Fix ghdl/ghdl-yosys-plugin#111Tristan Gingold2020-05-073-16/+36
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* synth-stmts: improve support of nested memories.Tristan Gingold2020-05-071-4/+5
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* synth: handle Pos attribute for booleans.Tristan Gingold2020-05-072-1/+2
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* synth: revert a previous commit: remove the En parameter.Tristan Gingold2020-05-0612-311/+226
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* synth-expr.adb: handle negative values. Fix ghdl/ghdl-yosys-plugin#115Tristan Gingold2020-05-061-2/+18
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* synth: add support for sequential assertions. Fix #1273Tristan Gingold2020-05-066-58/+312
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* netlists-folds: add Build2_And, remove default location.Tristan Gingold2020-05-063-13/+29
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* synth: add Id_Enable gate (for sequential assertions).Tristan Gingold2020-05-065-0/+25
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* vhdl-sem_expr: improve support of vhdl-08 aggregates. Fix #1282Tristan Gingold2020-05-051-24/+37
| | | | An element of an aggregate may have an unconstrained length.
* synth: revert part of sequential assertion support. Fix #1285Tristan Gingold2020-05-052-81/+20
| | | | | The idea of adding conditions to the sequential flow is incorrect. Need to add wires.
* synth: initial support of unbounded records. Fix #1283Tristan Gingold2020-05-057-11/+40
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* synth-aggre: propagate errors in record aggregate. Fix #1283Tristan Gingold2020-05-051-6/+14
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* vhdl-evaluation: handle record equality. For #1283Tristan Gingold2020-05-051-5/+127
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* synth: handle non-static vectors in target aggregates. Fix #1277Tristan Gingold2020-05-041-18/+71
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* synth: add comments.Tristan Gingold2020-05-042-2/+3
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* ghdldrv: add support for --time-resolution for -e. For #1281Tristan Gingold2020-05-041-8/+4
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