iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	synth: use original entity to display netlist.	Tristan Gingold	2019-07-23	7	-22/+314
*	vhdl-prints: improve output for ports/generics.	Tristan Gingold	2019-07-22	1	-5/+27
*	synth: remove bounds (unused) for ports.	Tristan Gingold	2019-07-22	4	-13/+4
*	ghdlsynth: preliminary work for wrapped generation.	Tristan Gingold	2019-07-22	1	-1/+8
*	synth: minor refactoring in netlists.disp_vhdl	Tristan Gingold	2019-07-22	2	-47/+54
*	synth: minor rework.	Tristan Gingold	2019-07-22	3	-10/+37
*	synth: rework names.	Tristan Gingold	2019-07-22	6	-24/+25
*	add port width utility function for yosys (#876)	Pepijn de Vos	2019-07-21	4	-0/+18
*	synth: improve output (id_extract).	Tristan Gingold	2019-07-20	1	-6/+12
*	synth: improve output (for id_insert).	Tristan Gingold	2019-07-20	1	-11/+18
*	synth: add support for concurrent selected signal assignment.	Tristan Gingold	2019-07-20	1	-2/+138
*	synth: support index of a constant.	Tristan Gingold	2019-07-20	1	-0/+4
*	synth: initial support for for-generate statement.	Tristan Gingold	2019-07-20	3	-34/+97
*	synth: add and merge phi within a function.	Tristan Gingold	2019-07-20	1	-0/+5
*	synth: fix aggregate vectorize direction.	Tristan Gingold	2019-07-20	2	-5/+6
*	synth: add concatn gate	Tristan Gingold	2019-07-19	9	-32/+126
*	synth: finalize concurrent assignments (WIP).	Tristan Gingold	2019-07-19	6	-33/+342
*	synth: add const_z gate.	Tristan Gingold	2019-07-19	4	-3/+33
*	errorout: handle %v for values.	Tristan Gingold	2019-07-19	2	-1/+36
*	synth: make more types private.	Tristan Gingold	2019-07-17	2	-35/+48
*	synth: make type Wire_Id_Record private.	Tristan Gingold	2019-07-17	7	-44/+74
*	synth: renaming of Assign to Seq_Assign.	Tristan Gingold	2019-07-17	6	-79/+82
*	synth: add comments.	Tristan Gingold	2019-07-17	2	-0/+2
*	vhdl: add a comment.	Tristan Gingold	2019-07-16	1	-0/+3
*	synth: add > and >= operators (#870)	Pepijn de Vos	2019-07-16	6	-25/+118
*	vhdl: avoid a crash on no matching operator error.	Tristan Gingold	2019-07-15	1	-1/+7
*	vhdl-sem_names: avoid a crash on parenthesis of	Tristan Gingold	2019-07-15	1	-2/+2
*	find_top_entity: avoid crash on missing entity, handle	Tristan Gingold	2019-07-15	2	-13/+27
*	synth: handle instantiation within generate statement.	Tristan Gingold	2019-07-15	1	-0/+2
*	ghdlsynth: quit early in case of error.	Tristan Gingold	2019-07-15	1	-1/+10
*	synth: handle choices by range in aggregates.	Tristan Gingold	2019-07-15	3	-12/+33
*	synth: handle anonymous subtypes in array subtypes.	Tristan Gingold	2019-07-15	1	-4/+10
*	synth: add comments.	Tristan Gingold	2019-07-15	1	-6/+10
*	synth: remove extra elaboration of port types.	Tristan Gingold	2019-07-15	1	-18/+2
*	synth: apply block configuration to for-generate statements.	Tristan Gingold	2019-07-15	1	-2/+15
*	synth: use correct instance to synth default expressions of assocs.	Tristan Gingold	2019-07-15	1	-10/+13
*	synth: save and restore instance_pool for processes.	Tristan Gingold	2019-07-15	1	-2/+4
*	synth: improve support of components (anon subtypes).	Tristan Gingold	2019-07-14	1	-0/+15
*	ghdlsynth: check top entity can be a top entity.	Tristan Gingold	2019-07-14	5	-23/+41
*	vhdl: refactoring: remove configure function with string access.	Tristan Gingold	2019-07-14	8	-105/+95
*	vhdl: set location on reference to the anonymous signal declaration.	Tristan Gingold	2019-07-14	1	-0/+1
*	ghdlsynth: automatically find top entity if not specified.	Tristan Gingold	2019-07-14	1	-8/+33
*	vhdl: fixes in find_top_entity (handle for-generate, remove early return)	Tristan Gingold	2019-07-14	2	-5/+27
*	synth: handle anonymous signals.	Tristan Gingold	2019-07-14	1	-0/+3
*	synth: handle black boxes.	Tristan Gingold	2019-07-13	3	-47/+108
*	synth: handle simple component instances.	Tristan Gingold	2019-07-13	1	-36/+256
*	vhdl: cleanup in clear_instantiation_configuration.	Tristan Gingold	2019-07-13	4	-70/+23
*	simul-elaboration: rewrite assertion.	Tristan Gingold	2019-07-13	1	-3/+3
*	vhdl-configuration: improve error message.	Tristan Gingold	2019-07-11	1	-1/+1
*	vhdl: minor reformating.	Tristan Gingold	2019-07-11	2	-8/+5