| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth-insts: add comments, minor refactoring. | Tristan Gingold | 2020-02-29 | 3 | -9/+6 |
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| * | synth: handle more physical operators. Fix #1146 | Tristan Gingold | 2020-02-29 | 4 | -21/+80 |
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| * | synth-static_oper: handle enum inequality. | Tristan Gingold | 2020-02-29 | 1 | -0/+3 |
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| * | synth-decls: fix handling of record subtypes. | Tristan Gingold | 2020-02-29 | 1 | -1/+14 |
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| * | vhdl-parse: improve error messages and recovery. | Tristan Gingold | 2020-02-27 | 1 | -8/+46 |
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| * | synth: handle file_close. | Tristan Gingold | 2020-02-27 | 3 | -10/+31 |
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| * | synth-static_oper: handle to_stdlogicvector_bv | Tristan Gingold | 2020-02-27 | 1 | -1/+20 |
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| * | Update copyright years before the release. | Tristan Gingold | 2020-02-26 | 1 | -1/+1 |
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| * | vhdl: handle CR+LF for readline in grt. Fix #1145 | Tristan Gingold | 2020-02-25 | 2 | -18/+62 |
| | | | | | | | | Previously CR+LF was handled in std.textio.readline. But that doesn't work if CR is at position 128 because we would need to read the next character. Now untruncated_text_read handles CR/CR+LF/LF and calls ungetc if needed. | ||||
| * | netlists: rework memories to fix port orders, add a loop. | Tristan Gingold | 2020-02-23 | 7 | -46/+85 |
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| * | netlists-memories: also reduce muxes for extract. | Tristan Gingold | 2020-02-21 | 1 | -7/+35 |
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| * | synth-decls: handle alias declaration without subtype indication. | Tristan Gingold | 2020-02-21 | 1 | -2/+7 |
| | | | | | Fix #1144 | ||||
| * | netlists-memories: factorize code. | Tristan Gingold | 2020-02-20 | 1 | -235/+191 |
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| * | netlists-inference: preliminary work to support else in synch code. | Tristan Gingold | 2020-02-20 | 1 | -71/+153 |
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| * | netlists: add midff | Tristan Gingold | 2020-02-20 | 3 | -0/+47 |
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| * | disable backtrace on android (#1142) | umarcor | 2020-02-19 | 1 | -1/+1 |
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| * | vhdl: recognize conversion functions from std_logic_1164 | Tristan Gingold | 2020-02-18 | 5 | -12/+70 |
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| * | synth: rework static predefined function calls. | Tristan Gingold | 2020-02-18 | 3 | -152/+224 |
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| * | synth: handle file_open. | Tristan Gingold | 2020-02-18 | 3 | -0/+48 |
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| * | synth-environment: handle unassigned outputs. | Tristan Gingold | 2020-02-18 | 1 | -6/+8 |
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| * | netlists-cleanup: refactoring. | Tristan Gingold | 2020-02-18 | 1 | -12/+17 |
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| * | synth-insts: handle slices in individual associations. | Tristan Gingold | 2020-02-18 | 1 | -0/+21 |
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| * | vhdl-sem_scopes: handle anonymous signal declarations. | Tristan Gingold | 2020-02-18 | 1 | -1/+2 |
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| * | vhdl-configuration: ignore configuration for top_level_entity. | Tristan Gingold | 2020-02-18 | 1 | -4/+4 |
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| * | synth-expr: handle anonymous signal declarations. | Tristan Gingold | 2020-02-18 | 2 | -6/+10 |
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| * | vhdl-sem_assocs: recurse for individual associations. | Tristan Gingold | 2020-02-17 | 1 | -23/+64 |
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| * | synth: allow constant condition for if-generate statement. | Tristan Gingold | 2020-02-17 | 1 | -0/+1 |
| | | | | | For #1076 | ||||
| * | synth: add mdff. | Tristan Gingold | 2020-02-17 | 4 | -12/+88 |
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| * | netlists-inference: remove useless code. | Tristan Gingold | 2020-02-16 | 1 | -10/+0 |
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| * | synthesis: rework memory inference. | Tristan Gingold | 2020-02-16 | 3 | -32/+101 |
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| * | synth: handle component with ports in different order. | Tristan Gingold | 2020-02-13 | 3 | -45/+46 |
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| * | vhdl-parse: improve recovery for incorrect end identifier. | Tristan Gingold | 2020-02-13 | 1 | -8/+27 |
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| * | files_maps-editor: fix incorrect assertion. | Tristan Gingold | 2020-02-13 | 1 | -1/+1 |
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| * | vhdl-sem_expr: avoid a crash on incorrect qualified expr. | Tristan Gingold | 2020-02-13 | 1 | -0/+6 |
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| * | synth-static_oper: handle more division operands. Fix #1134 | Tristan Gingold | 2020-02-12 | 1 | -1/+2 |
| | | | | | From donnie-j | ||||
| * | synth: handle null vector for vec-vec concat. Fix #1133 | Tristan Gingold | 2020-02-11 | 2 | -6/+12 |
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| * | synth-oper: handle add for (natural, unsigned). Fix #1132 | Tristan Gingold | 2020-02-11 | 1 | -0/+15 |
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| * | netlists-memories: handle split memories. Fix #1127 | Tristan Gingold | 2020-02-11 | 1 | -8/+18 |
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| * | translate: refine condition. Fix #1125 | Tristan Gingold | 2020-02-11 | 1 | -1/+1 |
| | | | | | For the check of matching direction in slices. | ||||
| * | synth-static_oper: handle xor. | Tristan Gingold | 2020-02-10 | 1 | -0/+11 |
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| * | synth-expr: implement value and val attributes. Fix #1130 | Tristan Gingold | 2020-02-10 | 1 | -1/+39 |
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| * | grt: split grt-errors, disp current process. | Tristan Gingold | 2020-02-10 | 18 | -104/+183 |
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| * | synth: remove remaining clock edge gates after memories. | Tristan Gingold | 2020-02-10 | 2 | -0/+26 |
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| * | netlists-memories: cleanup. | Tristan Gingold | 2020-02-10 | 1 | -319/+1 |
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| * | synth: rework (again) memory inference. | Tristan Gingold | 2020-02-10 | 8 | -80/+312 |
| | | | | | | | Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference. | ||||
| * | synth-inference: minor refactoring. | Tristan Gingold | 2020-02-06 | 1 | -24/+7 |
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| * | synth-decls: set a default value to non-assigned signals. Fix #1107 | Tristan Gingold | 2020-02-05 | 1 | -1/+3 |
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| * | netlists-disp_vhdl: handle 1-bit const_x. For #1107 | Tristan Gingold | 2020-02-05 | 1 | -3/+9 |
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| * | vhdl-sem_names: improve error location. | Tristan Gingold | 2020-02-04 | 1 | -1/+1 |
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| * | vhdl-sem: improve error location for unknown entity. | Tristan Gingold | 2020-02-04 | 1 | -1/+1 |
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index : iCE40/ghdl | |
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