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* vhdl-disp_tree: disp integer literal valueTristan Gingold2021-08-041-15/+27
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* vhdl-sem_expr.adb: build element subtype for aggregate when possible.Tristan Gingold2021-08-033-13/+164
| | | | | | | | In case of array aggregate whose element subtype is not bounded, extract it from the aggregate elements. Fix #1055 Fix #1455
* vhdl-parse: use if_generate_else_clause for elsif clauses. Fix #1824Tristan Gingold2021-07-291-1/+1
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* vhdl-sem_expr: analyze choices before expressions in array aggregate.Tristan Gingold2021-07-281-22/+39
| | | | | Avoid considering expression to be possibly of the type of the aggregate if the choice is an expression.
* vhdl: move check on instantiation name from sem to parse.Tristan Gingold2021-07-282-1/+4
| | | | Fix #1823
* vhdl-sem_stmts.adb: avoid a crash when forced analysis.Tristan Gingold2021-07-231-0/+4
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* vhdl-utils(free_recursive): only free the name (not the entity)Tristan Gingold2021-07-221-1/+1
| | | | Fix #1820
* vhdl-sem_assocs: improve handling of generic typesTristan Gingold2021-07-191-17/+21
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* trans-chap9: set line number for gcc. Fix #1817Tristan Gingold2021-07-191-2/+5
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* vhdl-evaluation: handle element attribute. Fix #1818Tristan Gingold2021-07-171-1/+2
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* vhdl-sem_stmts.adb: avoid a crash on invalid expressionTristan Gingold2021-07-051-1/+3
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* vhdl-sem_scopes.adb: consider operators for interface chainTristan Gingold2021-07-051-1/+2
| | | | | | A type interface also implicitly declares equality and inequality operators for the type. Adjust Add_Declaration_From_Interface_Chain so that these operators are visible
* adjust previous commit (no identifier in Psl_Default_Clock)Tristan Gingold2021-07-014-3/+5
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* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-305-107/+116
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* vhdl: handle mod/rem for physical. Fix #1810Tristan Gingold2021-06-304-1/+23
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* vhdl-nodes: do not reset free hooks on initializationTristan Gingold2021-06-263-2/+2
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* vhdl/Makefile: use python3 by defaultTristan Gingold2021-06-221-1/+1
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* vhdl-nodes: Initialize global state to allow restart.Tristan Gingold2021-06-192-0/+4
| | | | Fix handling of multiple files by cli/DOM.py
* vhdl-nodes.ads: use pnodes layout for Number_Base_TypeTristan Gingold2021-06-181-1/+8
| | | | So that it can be extracted.
* trans-chap3: add commentsTristan Gingold2021-06-071-2/+10
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* Fix warnings from gnatgpl 2021Tristan Gingold2021-05-301-1/+1
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* vhdl: avoid a crash on forced analysis of a erroneous name expressionTristan Gingold2021-05-282-22/+23
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* vhdl-sem_stmts.adb: avoid duplicate error messageTristan Gingold2021-05-281-0/+3
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* vhdl-utils: element attribute is a type markTristan Gingold2021-05-251-1/+2
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* vhdl-scanner: improve column for scanner messagesTristan Gingold2021-05-231-1/+4
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* vhdl-evaluation: add a commentTristan Gingold2021-05-221-0/+7
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* vhdl-evaluation: avoid a crash on null range for enumeration typesTristan Gingold2021-05-211-2/+60
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* trans-chap6: add a commentTristan Gingold2021-05-191-0/+1
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* vhdl-sem: handle indexed and slice names. Fix #1768Tristan Gingold2021-05-171-56/+42
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* vhdl-utils: an object alias may not have a subtype indication. Fix #1765Tristan Gingold2021-05-161-5/+10
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* vhdl: remove unused Get/Set_Alias_DeclarationTristan Gingold2021-05-165-127/+68
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* trans-chap4: add commentsTristan Gingold2021-05-161-0/+4
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* trans-chap6: handle alias of unbounded record. For #641Tristan Gingold2021-05-131-1/+2
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* vhdl-sem_stmts: handle aliases for force/release assignment. Fix #1751Tristan Gingold2021-05-061-5/+8
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* vhdl: handle object interface using an interface type. Fix #1726Tristan Gingold2021-04-173-4/+56
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* vhdl-sem_names: avoid a crash for invalid user attribute prefix. Fix #1727Tristan Gingold2021-04-161-1/+2
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* vhdl: also allow type and subtype declarations in vunit. For #1724Tristan Gingold2021-04-152-0/+4
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* vhdl-canon_psl: handle imp_boolTristan Gingold2021-04-151-2/+3
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* vhdl: handle constant declarations in PSL vunit. Fix #1724Tristan Gingold2021-04-152-0/+2
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* trans-chap9: handle N_Imp_Bool for PSL. For #1721Tristan Gingold2021-04-131-0/+21
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* vhdl-sem_psl.adb: can also extract clock from SERE. For #1721Tristan Gingold2021-04-131-1/+5
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* vhdl-sem_names.adb: fix check for object prefix of subtype attribute. Fix #1717Tristan Gingold2021-04-111-3/+1
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* src: Clarify error for conditional signal assignment.Ondrej Ille2021-04-111-1/+2
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* src: Allow case generate only in VHDL 2008.Ondrej Ille2021-04-111-0/+1
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* src: Unify check for VHDL at least 2008Ondrej Ille2021-04-111-47/+25
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* trans-chap9.adb: fix out of scope reference.Tristan Gingold2021-04-101-2/+3
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* ghdldrv,configure: allow LIB.UNIT name for -e/-r commands. Fix #1718Tristan Gingold2021-04-103-11/+38
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* src: Fix PSL start count assignment for PSL endpoints.Ondrej Ille2021-04-081-9/+9
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* src: Introduce two separate PSL counters (Finish and Start).Ondrej Ille2021-04-084-12/+43
| | | | | | Finish counter corresponds to legacy count. Start counter corresponds to number of times start state is left (assertion is triggered).
* src: Define PSL type RTI with simplified assertion state.Ondrej Ille2021-04-084-6/+94
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