iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	simul debugger: display packages and configuration.	Tristan Gingold	2016-03-10	1	-2/+12
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*	trans-chap12: refactor.	Tristan Gingold	2016-03-07	2	-53/+70
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*	translate: separate decl and stmt elab subprograms.	Tristan Gingold	2016-02-23	6	-96/+319
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*	translate: minor reformating.	Tristan Gingold	2016-02-21	1	-24/+19
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*	grt: remove rti field in signals (to reduce space).	Tristan Gingold	2016-02-21	1	-1/+0
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*	ortho: rename start/finish_const_value to start/finish_init_value.	Tristan Gingold	2016-02-21	8	-64/+64
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*	trans-chap12: factorize code.	Tristan Gingold	2016-02-20	1	-9/+1
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*	Refactoring in simulate in order to link with ortho.	Tristan Gingold	2016-02-20	16	-1213/+1307
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*	parse: detect early use of signature in expressions.	Tristan Gingold	2016-02-18	1	-1/+8
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*	parse: avoid weird error message for end protected.	Tristan Gingold	2016-02-17	1	-1/+8
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*	assocations: check rules for unconstrained formal (LRM08 5.3.2.2 e 3)	Tristan Gingold	2016-02-17	2	-4/+39
\| \| \| \|	Fix issue40
*	Tentative fix for issue43.	Tristan Gingold	2016-02-17	1	-1/+1
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*	Fix crash of issue42.	Tristan Gingold	2016-02-17	1	-1/+2
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*	simul debugger: add info instances	Tristan Gingold	2016-02-17	2	-3/+46
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*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-17	1	-2/+0
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*	PSL: move canon code to canon.adb	Tristan Gingold	2016-02-17	1	-0/+2
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*	simul: fix local protected object, boolean for-generate loop	Tristan Gingold	2016-02-14	3	-38/+51
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*	simul debugger: handle more concurrent statements.	Tristan Gingold	2016-02-14	1	-0/+50
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*	simul: more fixes for std_ulogic.	Tristan Gingold	2016-02-14	2	-17/+21
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*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	16	-78/+292
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*	simul: preliminary work to support PSL.	Tristan Gingold	2016-02-14	7	-105/+323
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*	PSL: move canon code to canon.adb	Tristan Gingold	2016-02-14	7	-135/+308
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*	simul: return the exit status set by std.env	Tristan Gingold	2016-02-14	1	-2/+4
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*	simul: check for no unconstrained port/generic of top-level entity.	Tristan Gingold	2016-02-14	2	-1/+30
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*	simul: make delayed signal elaborated.	Tristan Gingold	2016-02-10	1	-0/+1
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*	simul: add support of e8.	Tristan Gingold	2016-02-10	9	-170/+205
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*	simul: handle generic override.	Tristan Gingold	2016-02-10	3	-20/+106
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*	evaluation: handle whitespace for 'value.	Tristan Gingold	2016-02-10	3	-1/+54
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*	build_enumeration_value: correctly handle characters.	Tristan Gingold	2016-02-10	1	-12/+22
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*	simul: handle slice in individual association for subprograms.	Tristan Gingold	2016-02-10	1	-0/+11
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*	simul: fix type conversion to unconstrained array.	Tristan Gingold	2016-02-10	1	-14/+35
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*	simul: fix corner cases for image.	Tristan Gingold	2016-02-10	1	-100/+131
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*	simul: fix issue14.	Tristan Gingold	2016-02-10	1	-10/+21
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*	simul: fix elaboration check for implicit signals.	Tristan Gingold	2016-02-10	1	-0/+1
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*	simul: fix individual association for array.	Tristan Gingold	2016-02-09	1	-3/+4
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*	simul: add missing canon.	Tristan Gingold	2016-02-09	1	-3/+3
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*	simul: avoid stupid crashes in debugger.	Tristan Gingold	2016-02-09	1	-2/+10
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*	PSL: handle and/or in boolean assertion.	Tristan Gingold	2016-02-09	3	-19/+66
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*	Improve mixed dump of PSL and VHDL nodes.	Tristan Gingold	2016-02-09	2	-14/+16
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*	A subtype of a resolved array type is resolved.	Tristan Gingold	2016-02-06	1	-0/+3
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*	simul: handle vhdl 2008.	Tristan Gingold	2016-02-06	10	-164/+358
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*	simul: support of package instantiation.	Tristan Gingold	2016-02-06	4	-11/+85
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*	sem_inst: add a comment.	Tristan Gingold	2016-02-06	1	-0/+2
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*	simul: preliminary work for environments.	Tristan Gingold	2016-01-27	6	-80/+57
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*	translation: use Tables instead of GNAT.Table.	Tristan Gingold	2016-01-27	1	-4/+3
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*	simul: use Tables instead of GNAT.Table	Tristan Gingold	2016-01-27	5	-36/+24
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*	simul: handle declarations in configuration.	Tristan Gingold	2016-01-27	3	-59/+68
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*	simul: fix attribute specification, noop type conversion, indiv sig assoc.	Tristan Gingold	2016-01-26	5	-11/+37
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*	Fix check of conformance for physical units.	Tristan Gingold	2016-01-25	1	-1/+4
\| \| \| \|	Fix issue25
*	simul: handle default assignment to unconstrained ports.	Tristan Gingold	2016-01-24	3	-109/+63
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