aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl
Commit message (Collapse)AuthorAgeFilesLines
* vhdl: do not crash on attribute with a type conversion prefix.Tristan Gingold2019-09-041-2/+3
|
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-028-37/+40
|
* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-022-2/+6
|
* vhdl-annotations: ignore conditional variable assignment.Tristan Gingold2019-08-301-1/+2
|
* vhdl-annotate: handle shared anonymous subtype in interfaces.Tristan Gingold2019-08-301-1/+4
|
* vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-302-0/+39
|
* vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-302-5/+17
|
* synth: add support for record types.Tristan Gingold2019-08-291-0/+4
| | | | (WIP: need to fix regression of stmt01).
* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-271-0/+1
| | | | Fix tgingold/ghdlsynth-beta#40
* ignore restrict in simulation (#897)Pepijn de Vos2019-08-202-18/+17
|
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-202-5/+22
|
* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-206-66/+141
|
* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
|
* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-203-13/+53
|
* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
|
* vhdl: handle assume in verification units.Tristan Gingold2019-08-204-1/+9
|
* synth: handle verification units.Tristan Gingold2019-08-209-244/+411
|
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-1714-348/+530
|
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-1611-280/+549
|
* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-163-0/+15
|
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-152-0/+114
| | | | | | | | * add logic operators on unsigned * handle signed too * handle unary not
* vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.Tristan Gingold2019-08-141-0/+9
|
* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-147-78/+98
|
* vhdl-nodes_walk: handle iir_kind_psl_default_clock.Tristan Gingold2019-08-131-1/+2
|
* libghdl: also add synthesis part. For #884Tristan Gingold2019-08-131-0/+2
|
* libghdl: preliminary work to also support synth.Tristan Gingold2019-08-132-4/+9
|
* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-116-181/+206
|
* vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.Tristan Gingold2019-08-111-1/+24
| | | | Fix #885
* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-102-6/+36
| | | | Fix #886
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-107-63/+105
| | | | For #877
* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-095-304/+247
|
* vhdl: remove -Whides warnings for processes without a label.Tristan Gingold2019-08-081-0/+9
|
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-089-131/+154
|
* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-072-125/+91
|
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-0723-141/+293
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl: allow discrete subtype indication for discrete_range.Tristan Gingold2019-08-065-45/+53
| | | | For #877
* vhdl: for time resolution, do not consider unit name from textio body.Tristan Gingold2019-08-062-10/+38
| | | | For #881
* synth: improve support of vhdl08. Fix #882Tristan Gingold2019-08-051-1/+9
|
* synth: add support for memories.Tristan Gingold2019-07-291-0/+2
|
* synth: unconstrained arrays.Tristan Gingold2019-07-281-0/+3
|
* synth: preliminary support of dynamic indexing.Tristan Gingold2019-07-282-47/+70
|
* vhdl: linearize analyze and evaluation of concat operators.Tristan Gingold2019-07-265-360/+647
|
* vhdl+synth: recognize /= to std_logic_unsigned.Tristan Gingold2019-07-252-1/+13
|
* vhdl: handle (discard) more pragmas.Tristan Gingold2019-07-251-0/+8
|
* vhdl annotations: fix annotation of type in interface list.Tristan Gingold2019-07-241-0/+1
|
* vhdl scanner: handle pragma translate_on/translate_off.Tristan Gingold2019-07-242-4/+98
|
* vhdl: recognize resize function.Tristan Gingold2019-07-242-0/+38
|
* vhdl-prints: improve output for ports/generics.Tristan Gingold2019-07-221-5/+27
|
* synth: minor rework.Tristan Gingold2019-07-222-0/+14
|
* synth: initial support for for-generate statement.Tristan Gingold2019-07-201-5/+8
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 19:06:20 +0000