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* Synthesis of PSL built-in fell() function.tmeissner2020-06-071-0/+17
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* Synthesis of PSL built-in rose() function.tmeissner2020-06-061-0/+17
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* Synthesis of PSL stable() function.tmeissner2020-06-061-0/+17
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* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-1/+25
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* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-1/+1
| | | | Global renaming.
* vhdl-prints: handle evaluated expression for qualified_expression.Tristan Gingold2020-04-181-16/+19
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* psl: keep denoting names in the PSL ast.Tristan Gingold2020-03-131-1/+2
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* vhdl-prints: disable code to display anonymous signal.Tristan Gingold2020-03-021-2/+10
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* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-0/+2
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* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-8/+7
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-40/+89
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* ams-vhdl: handle record nature end name.Tristan Gingold2019-12-301-0/+2
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* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-1/+36
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* ams-vhdl: print subnature declarations.Tristan Gingold2019-12-301-1/+16
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* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-127/+405
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* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+2
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* vhdl-prints: subtype indication is optional in object alias.Tristan Gingold2019-12-261-3/+2
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* vhdl-prints: handle more constructs in psl vunit.Tristan Gingold2019-10-311-0/+5
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* vhdl-prints: do not crash on vunit declarations.Tristan Gingold2019-10-231-0/+4
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* psl: add active state.Tristan Gingold2019-10-211-0/+7
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* vhdl-prints: handle restrict in vunit.Tristan Gingold2019-10-211-0/+2
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* vhdl-prints: add parenthesis around boolean and/or.Tristan Gingold2019-10-181-0/+4
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-3/+4
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* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-201-1/+1
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* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
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* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
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* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-0/+13
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* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-141-6/+6
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* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-1/+5
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* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-101-0/+2
| | | | For #877
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-5/+4
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl-prints: improve output for ports/generics.Tristan Gingold2019-07-221-5/+27
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* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-6/+6
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* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-1/+18
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* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-0/+13
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* vhdl-prints: try to print error content.Tristan Gingold2019-06-041-0/+10
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* vhdl-prints: fix extra 'else' in disp_conditional_waveform.Tristan Gingold2019-06-031-2/+3
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* vhdl-prints: improve indent.Tristan Gingold2019-06-021-0/+4
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* vhdl-prints: improve output for if/then, architecture.Tristan Gingold2019-06-011-0/+4
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* vhdl-formatters: add indent.Tristan Gingold2019-06-011-1/+5
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* vhdl-prints: handle PSL, add psl tokens for strong and inclusive variants.Tristan Gingold2019-05-301-85/+394
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* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-0/+4155
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