iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl: check missing association to generics. Fix #1379	Tristan Gingold	2020-06-26	1	-0/+9
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*	vhdl: create default configuration for a vunit. Fix #1372	Tristan Gingold	2020-06-15	1	-158/+190
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*	vhdl: analyze and synth concurrent statements in vunit. Fix #1366	Tristan Gingold	2020-06-12	1	-7/+12
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*	psl: keep denoting names in the PSL ast.	Tristan Gingold	2020-03-13	1	-1/+2
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*	synth: simplify support of inertial associations.	Tristan Gingold	2020-01-09	1	-1/+1
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*	ams-vhdl: add simultaneous null statement.	Tristan Gingold	2019-12-30	1	-4/+23
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*	ams-vhdl: analyze, canon and print simultaneous procedural statements.	Tristan Gingold	2019-12-30	1	-0/+11
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*	vhdl-ams: fix tree consistency for subnature declaration.	Tristan Gingold	2019-12-29	1	-1/+2
\| \| \| \|	Also fix use and canon for it.
*	vhdl: improve support of AMS-vhdl (array and record natures, source quantities)	Tristan Gingold	2019-12-28	1	-2/+148
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*	vhdl: allow attributes in vunit declarations.	Tristan Gingold	2019-10-30	1	-1/+3
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*	vhdl-canon: handle simple signal assignment in vunits.	Tristan Gingold	2019-10-25	1	-273/+272
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*	vhdl-canon: extract canon_concurrent_label.	Tristan Gingold	2019-10-25	1	-20/+25
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*	vhdl-canon: handle some declarations in vunits.	Tristan Gingold	2019-10-23	1	-2/+18
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*	vhdl: Add the implicit [*] at start of PSL cover sequence.	Tristan Gingold	2019-10-15	1	-0/+7
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*	vhdl: handle cover and restrict within vunit.	Tristan Gingold	2019-10-15	1	-0/+4
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*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	1	-1/+1
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*	vhdl: handle assume in verification units.	Tristan Gingold	2019-08-20	1	-0/+2
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*	synth: handle verification units.	Tristan Gingold	2019-08-20	1	-31/+57
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*	vhdl: parse verification unit (WIP).	Tristan Gingold	2019-08-17	1	-0/+2
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*	vhdl: improve reprint of inertial association.	Tristan Gingold	2019-08-11	1	-27/+37
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*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-1/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	vhdl: cleanup in clear_instantiation_configuration.	Tristan Gingold	2019-07-13	1	-2/+2
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*	vhdl: minor reformating.	Tristan Gingold	2019-07-11	1	-3/+3
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*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-1/+1
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*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	1	-14/+26
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*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-13/+61
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*	vhdl: renames disp_vhdl to prints	Tristan Gingold	2019-05-30	1	-2/+2
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*	psl: add psl-types, psl-nodes_priv.	Tristan Gingold	2019-05-10	1	-0/+1
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*	Extract psl-errors from errorout.	Tristan Gingold	2019-05-10	1	-1/+2
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*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-0/+1
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*	vhdl: remove too strict assertion in canon. Fix #816	Tristan Gingold	2019-05-07	1	-11/+3
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*	vhdl-nodes_utils: renaming.	Tristan Gingold	2019-05-07	1	-13/+13
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*	vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling.	Tristan Gingold	2019-05-06	1	-11/+12
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*	vhdl: move iirs_utils to vhdl.utils	Tristan Gingold	2019-05-06	1	-1/+1
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*	vhdl: move sem* packages to vhdl children.	Tristan Gingold	2019-05-05	1	-3/+3
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*	vhdl: move canon to a vhdl child package.	Tristan Gingold	2019-05-05	1	-0/+3290