| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | src: Define PSL type RTI with simplified assertion state. | Ondrej Ille | 2021-04-08 | 1 | -0/+7 |
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| * | update license headers | umarcor | 2021-01-14 | 1 | -11/+9 |
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| * | translate: improve support of unbounded records and arrays. | Tristan Gingold | 2020-07-25 | 1 | -1/+1 |
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| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code | ||||
| * | Rework translation of unbounded and complex types. | Tristan Gingold | 2018-10-21 | 1 | -2/+2 |
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| * | unbounded records: add rti support (WIP) | Tristan Gingold | 2017-02-21 | 1 | -0/+2 |
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| * | vhdl08: add support of case-generate statement | Tristan Gingold | 2016-07-07 | 1 | -0/+1 |
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| * | PSL: add clocked SERE, make endpoints visible from VHDL. | Tristan Gingold | 2016-03-22 | 1 | -0/+1 |
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| * | PSL: add counters, generate rti and add --psl-report | Tristan Gingold | 2016-03-18 | 1 | -0/+1 |
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| * | Rework for vhdl08 generate: change rtis. | Tristan Gingold | 2015-01-04 | 1 | -0/+1 |
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| * | Split translation into child packages. | Tristan Gingold | 2014-11-09 | 1 | -0/+138 |
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index : iCE40/ghdl | |
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