iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl/trans: support suspend states	Tristan Gingold	2023-01-28	1	-0/+4
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*	vhdl: add support for file subtype. Fix #2174	Tristan Gingold	2022-08-11	1	-1/+2
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*	vhdl-nodes: renaming.	Tristan Gingold	2022-07-21	1	-3/+3
\| \| \| \| \| \| \|	Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
*	fix: avoid "unnecessary with of ancestor [-gnatwr]" with GCC 12	Xiretza	2022-05-14	1	-1/+1
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*	vhdl: remove iir_kind_anonymous_signal_declaration (now unused)	Tristan Gingold	2021-08-24	1	-6/+3
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*	src: Define PSL type RTI with simplified assertion state.	Ondrej Ille	2021-04-08	1	-6/+58
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*	update license headers	umarcor	2021-01-14	1	-11/+9
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*	trans-rtis: adjust max_depth of records. For #1404	Tristan Gingold	2020-08-26	1	-3/+7
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*	translate: improve support of unbounded records and arrays.	Tristan Gingold	2020-07-25	1	-3/+3
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*	ortho: add unbounded records, rework array subtypes.	Tristan Gingold	2020-07-25	1	-13/+23
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*	ortho: add a length parameter to start_array_aggr.	Tristan Gingold	2020-05-28	1	-20/+8
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*	vhdl: minimal support of interface package in entities. For #1262	Tristan Gingold	2020-04-27	1	-1/+2
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*	vhdl/translate: handle more partially constrained array subtypes. For #1038	Tristan Gingold	2020-01-06	1	-4/+2
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*	ignore restrict in simulation (#897)	Pepijn de Vos	2019-08-20	1	-3/+3
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*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-4/+12
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-4/+4
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*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-3/+6
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*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-1/+1
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*	vhdl: move iirs_utils to vhdl.utils	Tristan Gingold	2019-05-06	1	-1/+1
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*	vhdl: move configuration package as a vhdl child.	Tristan Gingold	2019-05-05	1	-2/+2
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*	trans-rtis: take into account instances in the count of packages.	Tristan Gingold	2018-11-24	1	-4/+15
\| \| \| \|	rtis: check number of packages.
*	trans-rtis: fix uninitialized variable.	Tristan Gingold	2018-10-24	1	-3/+8
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*	Rework translation of unbounded and complex types.	Tristan Gingold	2018-10-21	1	-122/+127
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*	translate: remove other use of Nam_Buffer.	Tristan Gingold	2018-01-20	1	-13/+7
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*	Rework array/record type mode to improve support of constrained records.	Tristan Gingold	2018-01-11	1	-15/+19
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*	Use flist for enumerations.	Tristan Gingold	2017-11-07	1	-2/+2
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*	Use Flist for records.	Tristan Gingold	2017-11-07	1	-3/+2
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*	Use Flist for array indexes.	Tristan Gingold	2017-11-06	1	-2/+2
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*	unbounded records: add rti support (WIP)	Tristan Gingold	2017-02-21	1	-55/+76
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*	vhdl08: allow PSL default clock declaration in block declarative parts.	Tristan Gingold	2017-01-13	1	-0/+5
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*	WIP for unconstrained records.	Tristan Gingold	2017-01-13	1	-1/+1
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*	translate: WIP - refactoring for unbounded records.	Tristan Gingold	2017-01-02	1	-1/+1
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*	translate: WIP for unbounded records.	Tristan Gingold	2017-01-02	1	-1/+1
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*	translate: refactoring for ortho_info_type.	Tristan Gingold	2016-12-30	1	-19/+19
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*	vhdl08: support top-level macro-expanded package instantiation declarations.	Tristan Gingold	2016-12-05	1	-4/+7
\| \| \| \|	Fixes #199
*	WIP for nested instantiation of macro-expansed packages.	Tristan Gingold	2016-11-12	1	-17/+23
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*	Add signal_attribute_declaration to hold implicit atribute signals.	Tristan Gingold	2016-10-08	1	-20/+29
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*	Rework range_expression and incomplete type for instantiation.	Tristan Gingold	2016-09-30	1	-3/+2
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*	vhdl08: strengthten nested packages.	Tristan Gingold	2016-09-12	1	-1/+8
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*	vhdl08: preliminary work to support nested package bodies.	Tristan Gingold	2016-09-04	1	-0/+11
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*	vhdl08: handle very simple nested packages.	Tristan Gingold	2016-09-03	1	-58/+76
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*	vhdl08: add support of case-generate statement	Tristan Gingold	2016-07-07	1	-16/+49
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*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	1	-3/+11
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*	PSL: add counters, generate rti and add --psl-report	Tristan Gingold	2016-03-18	1	-30/+51
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*	ortho: rename start/finish_const_value to start/finish_init_value.	Tristan Gingold	2016-02-21	1	-44/+44
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*	Pass signal values to interfaces. 'sigptr' optimization.	Tristan Gingold	2015-12-18	1	-1/+1
\| \| \| \|	Improve simulation speed by about 20%.
*	trans-rtis: fix uninitialized field (that could result in a crash).	Tristan Gingold	2015-09-15	1	-10/+8
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*	Replace fat accesses by bounds accesses	Tristan Gingold	2015-08-29	1	-19/+23
\| \| \| \| \|	translate: separate info for signals from object. Improve some error messages.
*	Handle vhdl08 if generate statements	Tristan Gingold	2015-01-07	1	-186/+302
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*	Rework for vhdl08 generate: change rtis.	Tristan Gingold	2015-01-04	1	-82/+193
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