iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	translate: add --no-elaboration flag	Tristan Gingold	2023-02-04	1	-1/+1
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*	translate: improve support for Flag_Elaboration	Tristan Gingold	2023-02-02	1	-1/+1
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*	translate: add a flag to disable elaboration	Tristan Gingold	2023-01-31	1	-2/+4
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*	vhdl/trans: support suspend states	Tristan Gingold	2023-01-28	1	-7/+17
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*	simul: handle PSL aborts	Tristan Gingold	2023-01-12	1	-0/+4
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*	trans-chap9.adb: destroy types in PSL expressions. For #2157	Tristan Gingold	2022-08-04	1	-3/+31
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*	trans-chap9.adb: handle async_abort, sync_abort. Fix #1654	Tristan Gingold	2021-08-30	1	-35/+111
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*	Rework inertial associations.	Tristan Gingold	2021-08-23	1	-12/+49
\| \| \| \| \|	Fix #1625 Fix #1672
*	vhdl: introduce iir_kind_association_element_by_name	Tristan Gingold	2021-08-06	1	-2/+1
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*	trans-chap9: set line number for gcc. Fix #1817	Tristan Gingold	2021-07-19	1	-2/+5
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*	vhdl-nodes: remove Identifier from Psl_Default_Clock	Tristan Gingold	2021-06-30	1	-3/+16
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*	trans-chap9: handle N_Imp_Bool for PSL. For #1721	Tristan Gingold	2021-04-13	1	-0/+21
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*	trans-chap9.adb: fix out of scope reference.	Tristan Gingold	2021-04-10	1	-2/+3
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*	src: Fix PSL start count assignment for PSL endpoints.	Ondrej Ille	2021-04-08	1	-9/+9
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*	src: Introduce two separate PSL counters (Finish and Start).	Ondrej Ille	2021-04-08	1	-9/+33
\| \| \| \| \| \|	Finish counter corresponds to legacy count. Start counter corresponds to number of times start state is left (assertion is triggered).
*	src: Define PSL type RTI with simplified assertion state.	Ondrej Ille	2021-04-08	1	-0/+26
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*	src: Move --psl-report-uncovered to run options, not analysis options.	Ondrej Ille	2021-03-22	1	-1/+1
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*	Revert "src: Add -Wpsl-uncovered option to optionally warn about uncovered ↵	Ondrej Ille	2021-03-22	1	-11/+9
\| \| \| \| \| \|	PSL sequences at the end of simulation." This reverts commit e20d4477f9b55f897d4f9008d6c94db8d8c3a54f.
*	Revert "src: Fix build warning for redundant comparison."	Ondrej Ille	2021-03-22	1	-1/+1
\| \| \| \|	This reverts commit 575d36067953ae20e76d64bc95d8b3c4577995db.
*	Revert "src: Fix notes on pull-request."	Ondrej Ille	2021-03-22	1	-1/+1
\| \| \| \|	This reverts commit c7a6eda4640ae235c944168ca6c536434808ece8.
*	src: Fix notes on pull-request.	Ondrej Ille	2021-03-22	1	-1/+1
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*	src: Fix build warning for redundant comparison.	Ondrej Ille	2021-03-22	1	-1/+1
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*	src: Add -Wpsl-uncovered option to optionally warn about uncovered PSL ↵	Ondrej Ille	2021-03-22	1	-9/+11
\| \| \| \|	sequences at the end of simulation.
*	update license headers	umarcor	2021-01-14	1	-11/+9
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*	vhdl: renaming in vhdl-canon.	Tristan Gingold	2020-08-08	1	-1/+1
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*	translate: minor changes.	Tristan Gingold	2020-08-04	1	-1/+1
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*	vhdl: parse and analyze force/release signal assignment statements.	Tristan Gingold	2020-08-01	1	-0/+1
\| \| \| \|	For #1416
*	ortho: add unbounded records, rework array subtypes.	Tristan Gingold	2020-07-25	1	-3/+3
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*	vhdl/translate: rework object type elaboration. For #641	Tristan Gingold	2020-06-24	1	-3/+3
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*	types: introduce Direction_Type, which replaces Iir_Direction.	Tristan Gingold	2020-04-20	1	-1/+1
\| \| \| \|	Global renaming.
*	vhdl: add scalar_size. Size of scalar types is computed during analysis.	Tristan Gingold	2020-04-06	1	-0/+1
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*	psl: keep denoting names in the PSL ast.	Tristan Gingold	2020-03-13	1	-1/+2
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*	ignore restrict in simulation (#897)	Pepijn de Vos	2019-08-20	1	-15/+14
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*	vhdl: remove severity from cover, report and severity from assume.	Tristan Gingold	2019-08-08	1	-4/+14
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*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-8/+21
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	vhdl/translate: reindent.	Tristan Gingold	2019-07-04	1	-1/+1
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*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-8/+8
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*	psl: add psl-types, psl-nodes_priv.	Tristan Gingold	2019-05-10	1	-0/+1
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*	vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.	Tristan Gingold	2019-05-10	1	-2/+2
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*	Extract psl-errors from errorout.	Tristan Gingold	2019-05-10	1	-1/+1
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*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-0/+1
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*	vhdl: move iirs_utils to vhdl.utils	Tristan Gingold	2019-05-06	1	-1/+1
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*	vhdl: move nodes_meta package to vhdl child.	Tristan Gingold	2019-05-06	1	-2/+2
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*	vhdl: move ieee packages to vhdl children.	Tristan Gingold	2019-05-05	1	-2/+2
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*	vhdl: move std_standard package to vhdl child.	Tristan Gingold	2019-05-05	1	-1/+1
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*	vhdl: move canon to a vhdl child package.	Tristan Gingold	2019-05-05	1	-2/+2
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*	Remove unused is_ref for choices. Adjust.	Tristan Gingold	2019-01-02	1	-4/+0
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*	translate: renaming of Kind_Expr/Get_Ortho_Expr.	Tristan Gingold	2018-12-11	1	-6/+7
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*	translate: refactoring.	Tristan Gingold	2018-11-20	1	-1/+1
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*	vhdl/translate: improve support of unbounded arrays.	Tristan Gingold	2018-11-09	1	-2/+2
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