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vhdl
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simulate
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Age
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*
simul: handle optional body for package instantiation.
Tristan Gingold
2017-12-07
1
-2
/
+5
|
*
simul: fix annotation of macro-expanded package instantiation.
Tristan Gingold
2017-12-07
1
-5
/
+16
|
*
simul: handle interface type.
Tristan Gingold
2017-12-07
2
-3
/
+6
|
*
simul: handle generic-mapped packages.
Tristan Gingold
2017-12-07
1
-4
/
+11
|
*
simul: handle nested package instantiation.
Tristan Gingold
2017-12-07
2
-2
/
+5
|
*
simul: fix execution of actual expression.
Tristan Gingold
2017-12-06
3
-13
/
+40
|
*
simul: remove Current_Component (unused).
Tristan Gingold
2017-12-06
2
-11
/
+3
|
*
simul: fix choice list for case generate statement.
Tristan Gingold
2017-12-05
1
-2
/
+4
|
*
simul: fix elaboration check for package.
Tristan Gingold
2017-12-05
1
-1
/
+5
|
*
simul: handle unconstrained case choice.
Tristan Gingold
2017-12-05
1
-1
/
+17
|
*
simul: psl default clock, unaffected waveform.
Tristan Gingold
2017-12-05
3
-0
/
+8
|
*
simul: handle interface subprogram.
Tristan Gingold
2017-12-05
3
-11
/
+26
|
*
simul: handle package interface, remove iir_value_environment.
Tristan Gingold
2017-12-05
9
-80
/
+25
|
*
simul: handle instantiated package.
Tristan Gingold
2017-12-05
4
-11
/
+46
|
*
simul: add support for case generate statetement.
Tristan Gingold
2017-12-04
4
-14
/
+68
|
*
simul: support nested packages.
Tristan Gingold
2017-12-04
2
-58
/
+71
|
*
simul: WIP for nested packages.
Tristan Gingold
2017-12-04
2
-3
/
+7
|
*
simul: add iir_value_instance, remove package_instances.
Tristan Gingold
2017-12-03
8
-35
/
+81
|
*
simul: Remove scope_type (unused).
Tristan Gingold
2017-12-03
4
-186
/
+14
|
*
simul: add global_info.
Tristan Gingold
2017-12-03
6
-63
/
+77
|
*
simul: refactoring: scope is now the corresponding sim_info.
Tristan Gingold
2017-12-03
8
-112
/
+119
|
*
Create the simul.ads package (for a namespace).
Tristan Gingold
2017-11-24
23
-77
/
+97
|
*
simulation: refactoring (move block_instance to iir_values).
Tristan Gingold
2017-11-24
11
-117
/
+113
|
*
Annotations: minor reformating.
Tristan Gingold
2017-11-19
2
-24
/
+15
|
*
ghdl_simul: handle obsoleted and optionnal package body.
Tristan Gingold
2017-11-18
1
-2
/
+14
|
*
ghdl_simul: use target bounds for variable assignment of an aggregate.
Tristan Gingold
2017-11-18
1
-3
/
+1
|
*
ghdl_simul: fix crash in elaboration.
Tristan Gingold
2017-11-18
1
-10
/
+7
|
*
simulate: add per signal id.
Tristan Gingold
2017-11-16
3
-2
/
+20
|
*
simulate: add port map.
Tristan Gingold
2017-11-16
3
-16
/
+29
|
*
simulate: add extra_slot.
Tristan Gingold
2017-11-16
2
-7
/
+22
|
*
list: update simulator.
Tristan Gingold
2017-11-11
3
-30
/
+31
|
*
Update simulate.
Tristan Gingold
2017-11-08
7
-79
/
+67
|
*
simulate: update (and revive).
Tristan Gingold
2017-10-24
6
-33
/
+87
|
*
ghdl_simul: also renames conversion.
Tristan Gingold
2017-09-13
3
-9
/
+27
|
*
Fix build error for ghdlsynth.
Tristan Gingold
2017-05-09
1
-1
/
+1
|
|
|
|
For #344
*
simulate: reorder block list, support Concurrent_Simple_Signal_Assignment
Tristan Gingold
2017-01-31
4
-25
/
+60
|
*
Fix ghdlsimul build.
Tristan Gingold
2017-01-31
2
-4
/
+5
|
*
ownership: fix ghdlsimul
Tristan Gingold
2016-12-12
4
-29
/
+56
|
*
simulation: remove sim_be after previous code factorization.
Tristan Gingold
2016-10-15
5
-199
/
+61
|
*
Rework AST to setup ownership and reference policy.
Tristan Gingold
2016-10-11
2
-4
/
+2
|
|
|
|
Check it with nodes_gc.
*
Rewrite most of error and warning messages.
Tristan Gingold
2016-08-02
2
-13
/
+14
|
*
Rewrite error messages.
Tristan Gingold
2016-08-02
1
-4
/
+3
|
*
Rewrite scan error messages: use formatting.
Tristan Gingold
2016-08-02
2
-9
/
+10
|
*
Rework warnings to have a uniq tag per warning.
Tristan Gingold
2016-08-01
1
-1
/
+2
|
*
Fix indentation and English mistakes.
Tristan Gingold
2016-07-05
1
-3
/
+3
|
*
simulate/execution: uses grt.strings
Tristan Gingold
2016-06-28
1
-5
/
+6
|
*
simulation: remove unused kind_range.
Tristan Gingold
2016-03-29
2
-9
/
+1
|
*
simulation: reuse Mode_Signal_Type from grt.types.
Tristan Gingold
2016-03-10
5
-72
/
+76
|
*
elaboration: use std_time to represent time in signal table.
Tristan Gingold
2016-03-10
3
-9
/
+9
|
*
simulation: add block id.
Tristan Gingold
2016-03-10
3
-1
/
+13
|
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