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* simul: handle optional body for package instantiation.Tristan Gingold2017-12-071-2/+5
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* simul: fix annotation of macro-expanded package instantiation.Tristan Gingold2017-12-071-5/+16
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* simul: handle interface type.Tristan Gingold2017-12-072-3/+6
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* simul: handle generic-mapped packages.Tristan Gingold2017-12-071-4/+11
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* simul: handle nested package instantiation.Tristan Gingold2017-12-072-2/+5
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* simul: fix execution of actual expression.Tristan Gingold2017-12-063-13/+40
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* simul: remove Current_Component (unused).Tristan Gingold2017-12-062-11/+3
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* simul: fix choice list for case generate statement.Tristan Gingold2017-12-051-2/+4
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* simul: fix elaboration check for package.Tristan Gingold2017-12-051-1/+5
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* simul: handle unconstrained case choice.Tristan Gingold2017-12-051-1/+17
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* simul: psl default clock, unaffected waveform.Tristan Gingold2017-12-053-0/+8
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* simul: handle interface subprogram.Tristan Gingold2017-12-053-11/+26
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* simul: handle package interface, remove iir_value_environment.Tristan Gingold2017-12-059-80/+25
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* simul: handle instantiated package.Tristan Gingold2017-12-054-11/+46
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* simul: add support for case generate statetement.Tristan Gingold2017-12-044-14/+68
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* simul: support nested packages.Tristan Gingold2017-12-042-58/+71
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* simul: WIP for nested packages.Tristan Gingold2017-12-042-3/+7
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* simul: add iir_value_instance, remove package_instances.Tristan Gingold2017-12-038-35/+81
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* simul: Remove scope_type (unused).Tristan Gingold2017-12-034-186/+14
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* simul: add global_info.Tristan Gingold2017-12-036-63/+77
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* simul: refactoring: scope is now the corresponding sim_info.Tristan Gingold2017-12-038-112/+119
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* Create the simul.ads package (for a namespace).Tristan Gingold2017-11-2423-77/+97
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* simulation: refactoring (move block_instance to iir_values).Tristan Gingold2017-11-2411-117/+113
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* Annotations: minor reformating.Tristan Gingold2017-11-192-24/+15
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* ghdl_simul: handle obsoleted and optionnal package body.Tristan Gingold2017-11-181-2/+14
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* ghdl_simul: use target bounds for variable assignment of an aggregate.Tristan Gingold2017-11-181-3/+1
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* ghdl_simul: fix crash in elaboration.Tristan Gingold2017-11-181-10/+7
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* simulate: add per signal id.Tristan Gingold2017-11-163-2/+20
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* simulate: add port map.Tristan Gingold2017-11-163-16/+29
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* simulate: add extra_slot.Tristan Gingold2017-11-162-7/+22
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* list: update simulator.Tristan Gingold2017-11-113-30/+31
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* Update simulate.Tristan Gingold2017-11-087-79/+67
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* simulate: update (and revive).Tristan Gingold2017-10-246-33/+87
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* ghdl_simul: also renames conversion.Tristan Gingold2017-09-133-9/+27
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* Fix build error for ghdlsynth.Tristan Gingold2017-05-091-1/+1
| | | | For #344
* simulate: reorder block list, support Concurrent_Simple_Signal_AssignmentTristan Gingold2017-01-314-25/+60
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* Fix ghdlsimul build.Tristan Gingold2017-01-312-4/+5
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* ownership: fix ghdlsimulTristan Gingold2016-12-124-29/+56
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* simulation: remove sim_be after previous code factorization.Tristan Gingold2016-10-155-199/+61
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* Rework AST to setup ownership and reference policy.Tristan Gingold2016-10-112-4/+2
| | | | Check it with nodes_gc.
* Rewrite most of error and warning messages.Tristan Gingold2016-08-022-13/+14
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* Rewrite error messages.Tristan Gingold2016-08-021-4/+3
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* Rewrite scan error messages: use formatting.Tristan Gingold2016-08-022-9/+10
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* Rework warnings to have a uniq tag per warning.Tristan Gingold2016-08-011-1/+2
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* Fix indentation and English mistakes.Tristan Gingold2016-07-051-3/+3
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* simulate/execution: uses grt.stringsTristan Gingold2016-06-281-5/+6
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* simulation: remove unused kind_range.Tristan Gingold2016-03-292-9/+1
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* simulation: reuse Mode_Signal_Type from grt.types.Tristan Gingold2016-03-105-72/+76
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* elaboration: use std_time to represent time in signal table.Tristan Gingold2016-03-103-9/+9
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* simulation: add block id.Tristan Gingold2016-03-103-1/+13
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