| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Create sem_lib from libraries. | Tristan Gingold | 2018-11-14 | 1 | -5/+6 |
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| * | Rename of Iir_Kinds_Library_Unit | Tristan Gingold | 2017-12-01 | 1 | -2/+2 |
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| * | Rework list implementation, use iterator. | Tristan Gingold | 2017-11-11 | 1 | -3/+5 |
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| * | Use flist for disconnection specification and component specification. | Tristan Gingold | 2017-11-08 | 1 | -4/+3 |
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| * | Use Flist for array indexes. | Tristan Gingold | 2017-11-06 | 1 | -1/+1 |
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| * | Improve error message for uninstantiated component. | Tristan Gingold | 2017-10-15 | 1 | -1/+3 |
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| * | Allow unbounded IN ports with relaxed rules. | Tristan Gingold | 2017-10-15 | 1 | -3/+6 |
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| * | Add ghdl --find-top command. | Tristan Gingold | 2017-07-05 | 1 | -0/+198 |
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| * | ownership: check tree after sem and canon. | Tristan Gingold | 2016-11-05 | 1 | -8/+9 |
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| * | canon: do not set formal of association by position. | Tristan Gingold | 2016-10-19 | 1 | -20/+40 |
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| * | Finish_Compilation: factorize code, move to libraries. | Tristan Gingold | 2016-10-15 | 1 | -16/+26 |
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| * | Comments and reformatting. | Tristan Gingold | 2016-09-14 | 1 | -9/+4 |
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| * | Rewrite most of error and warning messages. | Tristan Gingold | 2016-08-02 | 1 | -36/+27 |
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| * | Rewrite scan error messages: use formatting. | Tristan Gingold | 2016-08-02 | 1 | -15/+18 |
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| * | Rework warnings to have a uniq tag per warning. | Tristan Gingold | 2016-08-01 | 1 | -9/+12 |
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| * | vhdl08: add support of case-generate statement | Tristan Gingold | 2016-07-07 | 1 | -0/+13 |
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| * | Enable vest recursive instantiation test. | Tristan Gingold | 2016-07-03 | 1 | -3/+8 |
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| * | Initial support of direct recursive instantiation. | Tristan Gingold | 2016-07-03 | 1 | -4/+17 |
| | | | | | Fix issue #2. | ||||
| * | PSL: add clocked SERE, make endpoints visible from VHDL. | Tristan Gingold | 2016-03-22 | 1 | -0/+1 |
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| * | Refactoring in simulate in order to link with ortho. | Tristan Gingold | 2016-02-20 | 1 | -0/+14 |
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| * | Use WORK location for loading the elaborated unit. | Tristan Gingold | 2015-12-30 | 1 | -1/+2 |
| | | | | | This sets a real location for error messages. | ||||
| * | Fix elaboration order in case of recursive instantiation. | Tristan Gingold | 2015-12-03 | 1 | -2/+7 |
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| * | Replace fat accesses by bounds accesses | Tristan Gingold | 2015-08-29 | 1 | -2/+1 |
| | | | | | | translate: separate info for signals from object. Improve some error messages. | ||||
| * | Add context declaration and reference (vhdl 2008). | Tristan Gingold | 2015-05-12 | 1 | -3/+11 |
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| * | Allow generic without default values in top-level entity. | Tristan Gingold | 2015-05-11 | 1 | -1/+46 |
| | | | | | Implement ticket #47. | ||||
| * | Keep and handle simple name for Block_Specification. | Tristan Gingold | 2015-01-16 | 1 | -1/+1 |
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| * | Initial rework for vhdl 2008 generate statements. | Tristan Gingold | 2015-01-03 | 1 | -2/+15 |
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| * | configuration.adb: change for style. | Tristan Gingold | 2014-12-23 | 1 | -2/+1 |
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| * | Add comments. | Tristan Gingold | 2014-12-22 | 1 | -1/+6 |
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| * | Create src/vhdl subdirectory. | Tristan Gingold | 2014-11-04 | 1 | -0/+614 |
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index : iCE40/ghdl | |
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