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* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
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* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-113-4/+13
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* netlists-inference: detect false loops only for variables. Fix #2125Tristan Gingold2022-07-111-2/+3
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* netlists-disp_verilog: do not connect to null-range output. For #2113Tristan Gingold2022-07-081-41/+47
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* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
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* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
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* Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-051-1/+3
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* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
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* netlists-disp_verilog: handle Id_Abs. Fix #2113Tristan Gingold2022-07-041-1/+1
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* synth-vhdl_insts: also handled unbounded records in hash names.Tristan Gingold2022-07-021-0/+7
| | | | Fix #2119
* netlists-disp_verilog: adjust, discard null signals. For #2113Tristan Gingold2022-06-281-1/+6
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* netlists-disp_verilog: fix warningTristan Gingold2022-06-271-1/+2
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* synth/netlists-disp_verilog: skip null input port. Fix #2113Tristan Gingold2022-06-271-15/+20
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* synth: rework #2109 - remove null wiresTristan Gingold2022-06-277-26/+85
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* synth/netlists-disp_verilog: adjust previous patch. For #2109Tristan Gingold2022-06-271-1/+2
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* netlists-disp_verilog: do not display ports of width 0. Fix #2109Tristan Gingold2022-06-271-5/+19
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* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-162-4/+13
| | | | Fix #2099
* Add commentsTristan Gingold2022-06-151-1/+1
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* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-153-2/+28
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* src/synth: add netlists.rename to rename identifiers. Fix #2054Tristan Gingold2022-06-143-2/+130
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* netlists-disp_verilog: do not display blackboxes. Fix #2092Tristan Gingold2022-06-131-0/+5
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* netlists-disp_verilog: Use blocking assignments in non-clocked blocksAnton Blanchard2022-06-131-10/+10
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* synth-vhdl_insts: handle actual conversion function. Fix #2090Tristan Gingold2022-06-121-12/+38
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* elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089Tristan Gingold2022-06-122-7/+18
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* elab-vhdl_types(Synth_Array_Attribute): handle dimension parameterTristan Gingold2022-06-111-1/+3
| | | | Fix #2088
* synth-environment(Merge_Dyn_Insert): disable transformation.Tristan Gingold2022-06-111-1/+3
| | | | | | Do not transform a Dyn_Insert into a Dyn_Insert_En, to avoid spurious latch detection. For #2086
* netlists-memories: handle negation for In_Conjunction. Fix #2086Tristan Gingold2022-06-111-8/+3
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* synth-vhdl_eval: add support for more operationsTristan Gingold2022-06-111-1/+10
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* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-112-6/+23
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* elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtypeTristan Gingold2022-06-097-30/+64
| | | | Fix #2085
* vhdl-annotations: avoid a crash with subtype attribute in array.Tristan Gingold2022-06-092-3/+9
| | | | Fix #2084
* synth-vhdl_expr.adb: use base type for indexed names. Fix #2083Tristan Gingold2022-06-081-1/+2
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* synth-vhdl_expr: add an hook for signal attributesTristan Gingold2022-06-082-0/+11
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-071-8/+17
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* elab-vhdl_context: also handle generic subprogramsTristan Gingold2022-06-071-2/+6
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* errorout: add nowrite warning. Fix #2081Tristan Gingold2022-06-074-8/+11
| | | | During synthesis, emit a specific warning if a net is not assigned
* synth-vhdl_stmts: fix handling of instantiated subprogramsTristan Gingold2022-06-061-1/+3
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-061-1/+16
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* synth-vhdl_stmts: handle alias in assignment expressionTristan Gingold2022-06-063-2/+24
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* synth-vhdl_eval: recognize and handle to_stdulogicvectorTristan Gingold2022-06-061-2/+4
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-052-37/+112
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* synth-vhdl_eval: handle more operations (sgn/uns reduce)Tristan Gingold2022-06-051-6/+16
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* synth-vhdl-eval: handle more operationsTristan Gingold2022-06-054-31/+272
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* synth-vhdl_oper: handle more bit_vector operations. Fix #2074Tristan Gingold2022-06-051-8/+13
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* elab-debugger: add where commandTristan Gingold2022-06-051-28/+49
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* synth-vhdl_eval: handle rotations and shift for numeric_stdTristan Gingold2022-06-051-4/+40
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* synth-vhdl_eval: handle to_x01, to_ux01, to_x01z and is_xTristan Gingold2022-06-052-19/+56
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-053-2/+41
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* synth-ieee-numeric_std: fix handling of X for negationTristan Gingold2022-06-051-18/+20
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* synth-vhdl_eval: handle find_leftmost and find_rightmostTristan Gingold2022-06-053-0/+55
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