aboutsummaryrefslogtreecommitdiffstats
path: root/src/synth
Commit message (Collapse)AuthorAgeFilesLines
* synth: handle interface type in generics. For #412Tristan Gingold2021-12-153-25/+41
|
* Fix opening files relative to the current vhdlMatt Johnston2021-12-071-0/+2
| | | | | | | This regressed in 86fd1ab3 ("synth: do full elaboration before synthesis") 1 Nov 2021
* synth: add --latches option to enable latches. Fix #938Tristan Gingold2021-12-062-1/+8
|
* synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926Tristan Gingold2021-11-291-19/+11
|
* synth memories: also accept constant signal as memory initial valueTristan Gingold2021-11-282-4/+9
|
* elab-vhdl_objtypes.adb: add an assertionTristan Gingold2021-11-281-0/+2
|
* elab-vhdl_insts.adb: do not try to elaborate foreign instances twiceTristan Gingold2021-11-281-1/+6
|
* synth-vhdl_insts.adb: split synth_Instantiate_ModuleTristan Gingold2021-11-281-14/+26
|
* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-2810-32/+108
|
* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
|
* synth: put direction into port descTristan Gingold2021-11-178-31/+30
|
* synth: use a global table for instances attributesTristan Gingold2021-11-176-168/+117
|
* synth: renaming to instance_attributes.Tristan Gingold2021-11-1711-66/+72
|
* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
|
* synth: add ports attributesTristan Gingold2021-11-173-0/+120
|
* Add commentsTristan Gingold2021-11-171-0/+2
|
* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
|
* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
|
* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
|
* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
|
* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
|
* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
|
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-093-9/+14
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-052-25/+28
|
* synth: Support alias declarations in vunittmeissner2021-11-023-5/+14
|
* synth: do full elaboration before synthesisTristan Gingold2021-11-0158-1996/+5291
|
* synth: reject wait statement. Fix #1903Tristan Gingold2021-10-291-0/+3
|
* synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896Tristan Gingold2021-10-181-1/+5
|
* synth: Support PSL declarations in inline PSLtmeissner2021-10-141-1/+2
|
* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-131-2/+4
|
* synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886Tristan Gingold2021-10-101-42/+74
| | | | And add comments
* synth-vhdl_expr: fix handling of negative factor in slice. For #1886Tristan Gingold2021-10-091-25/+61
|
* synth-vhdl_decls.adb: also detect unassigned variables.Tristan Gingold2021-10-091-11/+4
| | | | For ghdl/ghdl-yosys-plugin#159
* netlists-disp_verilog: fix name for memory initializationTristan Gingold2021-09-281-3/+4
|
* netlists-disp_verilog: fix output of parameter assignments. Fix #1866Tristan Gingold2021-09-151-12/+12
|
* netlists-disp_verilog.adb: add 'parameter' before parameters declarationTristan Gingold2021-09-151-1/+1
| | | | For #1866
* synth/netlists-disp_verilog: fix output of parameter values. For #1866Tristan Gingold2021-09-153-12/+37
|
* vhdl: move Get_Source_Identifier to vhdl-utilsTristan Gingold2021-09-151-18/+0
|
* synth-vhdl_oper: handle nor for booleanTristan Gingold2021-09-141-0/+1
|
* vhdl-canon: recurse for default block configuration of a vunit.Tristan Gingold2021-09-121-7/+2
|
* synth-vhdl_stmts: fix crash on nested if-generate statement in vunits.Tristan Gingold2021-09-111-2/+5
| | | | Fix #1859
* vhdl: allow constants in vunit declarations. Fix #1856Tristan Gingold2021-09-081-0/+2
|
* netlists-cleanup: avoid crash when keep attribute value is a stringTristan Gingold2021-09-071-2/+39
|
* synth-vhdl_stmts.adb: do not expect configuration for vunit.Tristan Gingold2021-09-011-3/+3
| | | | For #1850
* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-313-10/+44
|
* synth-vhdl_stmts: fix a crash on never triggered PSL assertion.Tristan Gingold2021-08-291-0/+6
| | | | For #1832
* synth: improve result of is_positiveTristan Gingold2021-08-294-10/+15
|
* netlists-inference: improve location for dff.Tristan Gingold2021-08-291-1/+1
|
* synth: factorize code to create base instanceTristan Gingold2021-08-287-57/+104
|
* synthesis.adb: abstract instance_passesTristan Gingold2021-08-283-23/+34
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-12 20:10:38 +0000