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* synth-stmts: handle constant if statements.Tristan Gingold2020-03-071-0/+1
* netlists-builders: handle null operands for dyadic operations.Tristan Gingold2020-03-071-1/+0
* netlists-expands: fix dyn_insert_en (en was missing). Fix #1155Tristan Gingold2020-03-072-1/+4
* synthesis: handle initialized output ports.Tristan Gingold2020-03-077-25/+72
* netlists-disp_vhdl: handle xnor. Fix #1153Tristan Gingold2020-03-071-0/+2
* Remove redundant pragma inline.Tristan Gingold2020-03-061-1/+0
* synth: fix conversion of net to constant for physical values. Fix #1148Tristan Gingold2020-03-022-6/+11
* synth: top entity name is not anymore hashed by default.Tristan Gingold2020-03-015-81/+125
* synth-insts: add comments, minor refactoring.Tristan Gingold2020-02-293-9/+6
* synth: handle more physical operators. Fix #1146Tristan Gingold2020-02-294-21/+80
* synth-static_oper: handle enum inequality.Tristan Gingold2020-02-291-0/+3
* synth-decls: fix handling of record subtypes.Tristan Gingold2020-02-291-1/+14
* synth: handle file_close.Tristan Gingold2020-02-273-10/+31
* synth-static_oper: handle to_stdlogicvector_bvTristan Gingold2020-02-271-1/+20
* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-237-46/+85
* netlists-memories: also reduce muxes for extract.Tristan Gingold2020-02-211-7/+35
* synth-decls: handle alias declaration without subtype indication.Tristan Gingold2020-02-211-2/+7
* netlists-memories: factorize code.Tristan Gingold2020-02-201-235/+191
* netlists-inference: preliminary work to support else in synch code.Tristan Gingold2020-02-201-71/+153
* netlists: add midffTristan Gingold2020-02-203-0/+47
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-1/+2
* synth: rework static predefined function calls.Tristan Gingold2020-02-183-152/+224
* synth: handle file_open.Tristan Gingold2020-02-183-0/+48
* synth-environment: handle unassigned outputs.Tristan Gingold2020-02-181-6/+8
* netlists-cleanup: refactoring.Tristan Gingold2020-02-181-12/+17
* synth-insts: handle slices in individual associations.Tristan Gingold2020-02-181-0/+21
* synth-expr: handle anonymous signal declarations.Tristan Gingold2020-02-182-6/+10
* synth: allow constant condition for if-generate statement.Tristan Gingold2020-02-171-0/+1
* synth: add mdff.Tristan Gingold2020-02-174-12/+88
* netlists-inference: remove useless code.Tristan Gingold2020-02-161-10/+0
* synthesis: rework memory inference.Tristan Gingold2020-02-163-32/+101
* synth: handle component with ports in different order.Tristan Gingold2020-02-133-45/+46
* synth-static_oper: handle more division operands. Fix #1134Tristan Gingold2020-02-121-1/+2
* synth: handle null vector for vec-vec concat. Fix #1133Tristan Gingold2020-02-112-6/+12
* synth-oper: handle add for (natural, unsigned). Fix #1132Tristan Gingold2020-02-111-0/+15
* netlists-memories: handle split memories. Fix #1127Tristan Gingold2020-02-111-8/+18
* synth-static_oper: handle xor.Tristan Gingold2020-02-101-0/+11
* synth-expr: implement value and val attributes. Fix #1130Tristan Gingold2020-02-101-1/+39
* synth: remove remaining clock edge gates after memories.Tristan Gingold2020-02-102-0/+26
* netlists-memories: cleanup.Tristan Gingold2020-02-101-319/+1
* synth: rework (again) memory inference.Tristan Gingold2020-02-108-80/+312
* synth-inference: minor refactoring.Tristan Gingold2020-02-061-24/+7
* synth-decls: set a default value to non-assigned signals. Fix #1107Tristan Gingold2020-02-051-1/+3
* netlists-disp_vhdl: handle 1-bit const_x. For #1107Tristan Gingold2020-02-051-3/+9
* synth-inference: use the mux output to detect end of walk. Fix #1122Tristan Gingold2020-02-011-1/+8
* synth-oper: handle std_match for slv. Close #1121Tristan Gingold2020-01-311-1/+2
* netlists-expands: also handle ror.Tristan Gingold2020-01-301-7/+24
* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-305-1/+154
* netlists-disp_vhdl: minor rework.Tristan Gingold2020-01-261-2/+2
* synth: convert subtype on return. Fix #1116Tristan Gingold2020-01-261-1/+1
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