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* synth: fix handling of record constraints in subtype. Fix #1961Tristan Gingold2022-02-221-1/+9
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* elab-vhdl_values.adb: fix a typo. Fix #1968Tristan Gingold2022-02-181-2/+2
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* synth-vhdl_oper: handle to_unsigned with an unsigned for size. Fix #1977Tristan Gingold2022-02-171-27/+30
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* synth: properly propagate bound errors. Fix #1972Tristan Gingold2022-02-174-16/+38
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* synth-vhdl_oper: handle bit condition operator. Fix #1971Tristan Gingold2022-02-161-1/+2
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* synth-vhdl_aggr: fix mismatch. Fix #1962Tristan Gingold2022-02-051-1/+6
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* synth: fix handling of std_logic_unsigned."-" for negative numbers.Tristan Gingold2022-01-181-8/+12
| | | | Fix #1951
* synth: adjust handling of subprogram calls in package instantiation. Fix #1947Tristan Gingold2022-01-161-3/+14
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* synth: do not annotate generic types in package. Fix #1949Tristan Gingold2022-01-151-11/+19
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* synth: handle macro-expanded package body. Fix #1948Tristan Gingold2022-01-142-2/+4
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* synth: handle alias of alias. Fix #1945Tristan Gingold2022-01-121-2/+15
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* synth: refine handling of interface type. Fix #1944Tristan Gingold2022-01-101-2/+6
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* synth: ignore use clauses in finalization Fix #1942Tristan Gingold2022-01-051-0/+2
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* synth: handle package instantiation in declarations. Fix #1938Tristan Gingold2022-01-034-1/+12
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* synth: add assertionsTristan Gingold2021-12-191-0/+4
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* ghdldrv: fix crash due to double initializationTristan Gingold2021-12-191-2/+0
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* synth: handle interface type in generics. For #412Tristan Gingold2021-12-153-25/+41
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* Fix opening files relative to the current vhdlMatt Johnston2021-12-071-0/+2
| | | | | | | This regressed in 86fd1ab3 ("synth: do full elaboration before synthesis") 1 Nov 2021
* synth: add --latches option to enable latches. Fix #938Tristan Gingold2021-12-062-1/+8
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* synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926Tristan Gingold2021-11-291-19/+11
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* synth memories: also accept constant signal as memory initial valueTristan Gingold2021-11-282-4/+9
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* elab-vhdl_objtypes.adb: add an assertionTristan Gingold2021-11-281-0/+2
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* elab-vhdl_insts.adb: do not try to elaborate foreign instances twiceTristan Gingold2021-11-281-1/+6
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* synth-vhdl_insts.adb: split synth_Instantiate_ModuleTristan Gingold2021-11-281-14/+26
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* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-2810-32/+108
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* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
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* synth: put direction into port descTristan Gingold2021-11-178-31/+30
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* synth: use a global table for instances attributesTristan Gingold2021-11-176-168/+117
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* synth: renaming to instance_attributes.Tristan Gingold2021-11-1711-66/+72
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* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
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* synth: add ports attributesTristan Gingold2021-11-173-0/+120
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* Add commentsTristan Gingold2021-11-171-0/+2
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* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
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* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
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* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
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* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
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* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
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* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
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* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-093-9/+14
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-052-25/+28
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* synth: Support alias declarations in vunittmeissner2021-11-023-5/+14
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* synth: do full elaboration before synthesisTristan Gingold2021-11-0158-1996/+5291
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* synth: reject wait statement. Fix #1903Tristan Gingold2021-10-291-0/+3
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* synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896Tristan Gingold2021-10-181-1/+5
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* synth: Support PSL declarations in inline PSLtmeissner2021-10-141-1/+2
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* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-131-2/+4
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* synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886Tristan Gingold2021-10-101-42/+74
| | | | And add comments
* synth-vhdl_expr: fix handling of negative factor in slice. For #1886Tristan Gingold2021-10-091-25/+61
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* synth-vhdl_decls.adb: also detect unassigned variables.Tristan Gingold2021-10-091-11/+4
| | | | For ghdl/ghdl-yosys-plugin#159
* netlists-disp_verilog: fix name for memory initializationTristan Gingold2021-09-281-3/+4
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