| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | synth: handle slice assignment. | Tristan Gingold | 2019-06-25 | 1 | -0/+12 | |
| * | synth: remove unused Value_Logic. | Tristan Gingold | 2019-06-23 | 1 | -10/+0 | |
| * | synth: handle more predefined functions. | Tristan Gingold | 2019-06-23 | 1 | -8/+19 | |
| * | synth: get rid of execution and elaboration. | Tristan Gingold | 2019-06-19 | 1 | -53/+179 | |
| * | synth: support conditional signal assignments. | Tristan Gingold | 2019-06-08 | 1 | -0/+11 | |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+144 | |
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index : iCE40/ghdl | |
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