| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | synth: add Id_Port gate to improve display. | Tristan Gingold | 2019-07-10 | 1 | -2/+5 | |
| * | synth: handle instantiation (WIP) | Tristan Gingold | 2019-07-10 | 1 | -0/+478 | |
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index : iCE40/ghdl | |
| [no description] |
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