| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: rework (again) memory inference. | Tristan Gingold | 2020-02-10 | 1 | -0/+40 |
| Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference. | |||||
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index : iCE40/ghdl | |
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