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* Add parsing of case? statement and simple test.Brian Padalino2021-09-2413-317/+465
| | | | Also add the Matching flag to the Iir_Kind_Case_Statement.
* ghdldrv: use environment variable CC to set the default compiler. For #1629Tristan Gingold2021-09-231-3/+6
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* testsuite/gna: add a test for #1875Tristan Gingold2021-09-232-0/+30
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* vhdl-ieee-vital_timing.adb: handle vhdl 2008. Fix #1875Tristan Gingold2021-09-231-3/+15
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* vhdl-evaluation.adb: Minor style fixesTristan Gingold2021-09-231-60/+61
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* vhdl-sem_assocs.adb: add commentsTristan Gingold2021-09-231-10/+41
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* Add test for matching operators.Brian Padalino2021-09-232-0/+180
| | | | Add an exhaustive test for the matching operators.
* testsuite/pyunit/lsp/LanguageServer: fix pastoumarcor2021-09-231-10/+2
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* ci: run macOS 10.15 and 11.0 (#1630)eine2021-09-231-5/+8
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* scripts/vendors: fix PoSh scripting (#1878)Unai Martinez-Corral2021-09-227-13/+13
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| * Fixed it also in other vendor scripts. Fixed verbosity level.Patrick Lehmann2021-09-225-9/+9
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| * Fixed parameter types and how to pass boolean/switch parameters from PoSh ↵Patrick Lehmann2021-09-223-4/+4
| | | | | | | | script to PoSh script.
* | Add explicit ?>= and ?> functions for translation.Brian Padalino2021-09-226-4/+30
|/ | | | | | Instead of swapping L/R arguments to try to create ?>= and ?>, create a function for each which performs the not operation of ?< and ?<= as defined by the LRM.
* Implement Matching Operators (#1872)Brian Padalino2021-09-221-8/+148
| | | Implement the matching operators ?<, ?<=, ?>, ?>=, ?/=.
* testsuite/gna: add a test for #543Tristan Gingold2021-09-183-0/+38
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* vhdl-evaluation.adb: handle iir_kind_aggregate in build_constant. Fix #543Tristan Gingold2021-09-181-0/+11
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* vhdl-parse.adb: minor reformattingTristan Gingold2021-09-181-1/+2
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* testsuite/gna: add a test for #1514Tristan Gingold2021-09-182-0/+22
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* trans-chap8: fix iteration on an enumeration type with only one literal.Tristan Gingold2021-09-181-3/+9
| | | | Fix #1514
* trans-chap8.adb: refactoring and clean-up. For #1514Tristan Gingold2021-09-182-46/+12
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* vhdl-sem_names(sem_parenthesis_name): minor refactoringTristan Gingold2021-09-181-13/+9
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* testsuite/gna: add a test for #1515Tristan Gingold2021-09-182-0/+21
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* vhdl-sem_names(sem_parenthesis_name): handle indexing of delayed attribute.Tristan Gingold2021-09-181-2/+6
| | | | Fix #1515
* configure and Makefile: link ghdl with grt-cstdioTristan Gingold2021-09-175-8/+13
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* vhdl-evaluation.adb: fix warningTristan Gingold2021-09-171-3/+0
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* testsuite/gna: add a test for #874Tristan Gingold2021-09-172-0/+39
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* vhdl-evaluation: implement to_string for real with format. Fix #874Tristan Gingold2021-09-171-23/+69
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* testsuite/gna: add a test and close #757Tristan Gingold2021-09-172-0/+22
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* pyGHDL: added binding to new function 'Get_Source_Identifier' (#1870)Unai Martinez-Corral2021-09-162-2/+52
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| * Use new 'Get_Source_Identifier' in pyGHDL.DOM.Patrick Lehmann2021-09-161-2/+2
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| * Added binding to new function 'Get_Source_Identifier'.Patrick Lehmann2021-09-161-0/+50
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* vhdl-utils: minor renaming for homogeneityTristan Gingold2021-09-162-2/+2
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* testsuite/gna: add a test for #1857Tristan Gingold2021-09-163-0/+55
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* trans-chap4: handle unbounded aggregate initial value to unbounded signal.Tristan Gingold2021-09-161-1/+30
| | | | Fix #1857
* testsuite/gna: add a test for #1867Tristan Gingold2021-09-162-0/+47
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* Fixed some typos (#1868)Patrick Lehmann2021-09-1611-22/+22
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* netlists-disp_verilog: fix output of parameter assignments. Fix #1866Tristan Gingold2021-09-151-12/+12
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* netlists-disp_verilog.adb: add 'parameter' before parameters declarationTristan Gingold2021-09-151-1/+1
| | | | For #1866
* synth/netlists-disp_verilog: fix output of parameter values. For #1866Tristan Gingold2021-09-153-12/+37
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* testsuite/gna: add a test and close #1495Tristan Gingold2021-09-152-0/+29
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* vhdl: move Get_Source_Identifier to vhdl-utilsTristan Gingold2021-09-153-18/+25
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* testsuite/gna: add a test for #1864Tristan Gingold2021-09-142-0/+30
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* ortho_code-x86-insns: handle OE_ADD R_I_Off + R_I. Fix #1864Tristan Gingold2021-09-141-0/+7
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* testsuite/gna: add a test and close #913Tristan Gingold2021-09-143-0/+51
| | | | Also close #926 (looks similar, but without a proper reproducer)
* testsuite/gna: add a test and close #737Tristan Gingold2021-09-141-1/+2
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* vhdl-sem_expr.adb: adjust aggregate element type extraction. For #737Tristan Gingold2021-09-141-2/+7
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* testsuite/gna: add a test for #1493Tristan Gingold2021-09-142-0/+30
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* trans-chap7: improve handling of vector in aggregates. Fix #1493Tristan Gingold2021-09-141-32/+58
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* synth-vhdl_oper: handle nor for booleanTristan Gingold2021-09-141-0/+1
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* trans-chap3: improve commentTristan Gingold2021-09-141-4/+4
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