| Commit message (Expand) | Author | Age | Files | Lines |
... | |
* | | synth: add support for --synth on llvm, link with -lm. | Tristan Gingold | 2019-08-30 | 2 | -0/+6 |
* | | synth: fix type elaboration of interfaces. | Tristan Gingold | 2019-08-30 | 1 | -2/+0 |
* | | synth: remove unused const gates. | Tristan Gingold | 2019-08-30 | 2 | -13/+5 |
* | | vhdl-annotations: ignore conditional variable assignment. | Tristan Gingold | 2019-08-30 | 1 | -1/+2 |
* | | vhdl-annotate: handle shared anonymous subtype in interfaces. | Tristan Gingold | 2019-08-30 | 1 | -1/+4 |
* | | synth: ignore report statement. | Tristan Gingold | 2019-08-30 | 1 | -0/+2 |
* | | vhdl: recognize ieee.numeric_std std_match. | Tristan Gingold | 2019-08-30 | 4 | -196/+241 |
* | | std_names: add std_match | Tristan Gingold | 2019-08-30 | 2 | -3/+5 |
* | | vhdl: recognize 1164 condition operator, handle in synth. | Tristan Gingold | 2019-08-30 | 5 | -114/+137 |
* | | synth: handle enumeration subtype in ranges. | Tristan Gingold | 2019-08-30 | 1 | -1/+2 |
* | | synth: fix named association in record aggregate. | Tristan Gingold | 2019-08-30 | 1 | -1/+3 |
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* | testsuite/synth: add testcase for records. Temporary disable stmt01 | Tristan Gingold | 2019-08-29 | 5 | -0/+168 |
* | synth: add support for record types. | Tristan Gingold | 2019-08-29 | 13 | -82/+361 |
* | synth: Integer operators (#902) | marph91 | 2019-08-28 | 3 | -0/+47 |
* | testsuite/synth: testcase for conditional signal assignment. | Tristan Gingold | 2019-08-27 | 3 | -0/+61 |
* | synth: support sequential conditional signal assignment. | Tristan Gingold | 2019-08-27 | 2 | -0/+3 |
* | testsuite/synth: add cases for assign. | Tristan Gingold | 2019-08-27 | 4 | -4/+62 |
* | testsuite/synth: add asgn01 | Tristan Gingold | 2019-08-27 | 5 | -0/+124 |
* | synth: rework partial assignments | Tristan Gingold | 2019-08-27 | 10 | -182/+608 |
* | netlists-disp_vhdl: do not used literals for prefixes. | Tristan Gingold | 2019-08-27 | 1 | -12/+53 |
* | Makefile.in: Add .NOTPARALLEL. For #888 | Tristan Gingold | 2019-08-27 | 1 | -0/+9 |
* | testsuite/synth: add fsm02 test. | Tristan Gingold | 2019-08-27 | 5 | -0/+181 |
* | ignore restrict in simulation (#897) | Pepijn de Vos | 2019-08-20 | 2 | -18/+17 |
* | synth: add support for constant exponentiation. | Tristan Gingold | 2019-08-20 | 1 | -0/+10 |
* | synth: set name to assert/assume gates. | Tristan Gingold | 2019-08-20 | 4 | -12/+44 |
* | netlist: fix minor pasto. | Tristan Gingold | 2019-08-20 | 1 | -1/+1 |
* | initial support for reduce and/or (#900) | Pepijn de Vos | 2019-08-20 | 7 | -6/+77 |
* | vhdl psl: fully scan PSL keywords in scanner. | Tristan Gingold | 2019-08-20 | 7 | -67/+148 |
* | vhdl-prints: handle architecture in verification unit hierarchical name. | Tristan Gingold | 2019-08-20 | 1 | -0/+7 |
* | testsuite/synth: add a test for previous commit. | Tristan Gingold | 2019-08-20 | 2 | -0/+13 |
* | vhdl: handle architecture in verification unit hierarchical name. | Tristan Gingold | 2019-08-20 | 3 | -13/+53 |
* | vhdl-prints: handle verification units. | Tristan Gingold | 2019-08-20 | 1 | -318/+354 |
* | testsuite/synth: add a test for assume directive in verification units. | Tristan Gingold | 2019-08-20 | 2 | -2/+11 |
* | vhdl: handle assume in verification units. | Tristan Gingold | 2019-08-20 | 5 | -1/+11 |
* | testsuite/synth: add psl02 | Tristan Gingold | 2019-08-20 | 4 | -0/+74 |
* | synth: analyze input files. | Tristan Gingold | 2019-08-20 | 1 | -1/+8 |
* | synth: set location on assume/assert gates. | Tristan Gingold | 2019-08-20 | 3 | -8/+19 |
* | synth: handle verification units. | Tristan Gingold | 2019-08-20 | 15 | -491/+703 |
* | synth: handle array attribute "length" (#895) | marph91 | 2019-08-19 | 1 | -0/+10 |
* | synth: add testcase for issue 34 | Tristan Gingold | 2019-08-17 | 13 | -0/+442 |
* | synth: fix tgingold/ghdlsynth#34 (association). | Tristan Gingold | 2019-08-17 | 1 | -2/+1 |
* | vhdl: parse verification unit (WIP). | Tristan Gingold | 2019-08-17 | 16 | -605/+792 |
* | testsuite/synth: add reproducer for tgingold/ghdlsynth-beta#33 | Tristan Gingold | 2019-08-16 | 3 | -0/+73 |
* | synth: handle integer values in subtype conversion. | Tristan Gingold | 2019-08-16 | 1 | -0/+2 |
* | synth: handle integers for displaying vhdl ports. | Tristan Gingold | 2019-08-16 | 1 | -0/+10 |
* | vhdl: declare verification units (WIP). | Tristan Gingold | 2019-08-16 | 15 | -759/+1061 |
* | testsuite: strenghten a testcase. | Tristan Gingold | 2019-08-16 | 1 | -0/+1 |
* | vhdl: recognize PSL units reserved words. | Tristan Gingold | 2019-08-16 | 9 | -737/+774 |
* | testsuite/python: fix test name (to follow the testsuite.sh convention) | Tristan Gingold | 2019-08-16 | 3 | -0/+0 |
* | synth: handle array attributes; handle integer subtypes in generics. | Tristan Gingold | 2019-08-16 | 2 | -2/+91 |