iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: add netlists-memories to extract memories. Still WIP.	Tristan Gingold	2019-10-17	8	-18/+553
\|
*	netlists: add remove_instance.	Tristan Gingold	2019-10-16	2	-0/+35
\|
*	vhdl: check cover/restrict is followed by a sequence.	Tristan Gingold	2019-10-16	4	-11/+65
\|
*	synth: fix psl cover - test when the final state is reached.	Tristan Gingold	2019-10-15	1	-3/+14
\|
*	vhdl: Add the implicit [*] at start of PSL cover sequence.	Tristan Gingold	2019-10-15	3	-0/+37
\|
*	vhdl: handle cover and restrict within vunit.	Tristan Gingold	2019-10-15	5	-1/+17
\|
*	synth: handle overflow literal.	Tristan Gingold	2019-10-15	2	-1/+9
\|
*	netlists: declare memory gates.	Tristan Gingold	2019-10-15	3	-3/+215
\|
*	synth-expr: handle any discrete_range in aggregate choices.	Tristan Gingold	2019-10-15	1	-1/+2
\|
*	testsuite/synth: add testcase for previous commit.	Tristan Gingold	2019-10-15	6	-0/+118
\|
*	synth-insts: accept architecture instantiation in synth_dependencies.	Tristan Gingold	2019-10-15	1	-2/+3
\|
*	Use Decode_Work_Option in options. Factorize code.	Tristan Gingold	2019-10-15	4	-25/+11
\|
*	testsuite/synth: add a test for --work option within files.	Tristan Gingold	2019-10-15	4	-0/+75
\|
*	ghdlsynth: allow --work= option in the middle of files.	Tristan Gingold	2019-10-15	3	-1/+48
\|
*	testsuite/synth: add a test.	Tristan Gingold	2019-10-15	3	-1/+68
\|
*	testsuite/synth: add a test for previous commit.	Tristan Gingold	2019-10-14	3	-1/+87
\|
*	synth-inference: handle multiple connections.	Tristan Gingold	2019-10-14	1	-14/+31
\|
*	testsuite/synth: add testcases for previous commit.	Tristan Gingold	2019-10-14	13	-0/+494
\|
*	synth-infere: extract clock from and tree.	Tristan Gingold	2019-10-14	1	-17/+102
\|
*	netlists-dump: do not print name of anonymous parameters.	Tristan Gingold	2019-10-14	1	-2/+6
\|
*	testsuite/synth: add testcase for previous commit.	Tristan Gingold	2019-10-14	3	-1/+80
\|
*	synth-infere: fix partial assignment with clock enable.	Tristan Gingold	2019-10-14	1	-2/+9
\|
*	vhdl-evaluation: handle bit condition operator. Fix #977	Tristan Gingold	2019-10-13	1	-0/+3
\|
*	synth: handle constants for condition operator.	Tristan Gingold	2019-10-13	3	-1/+20
\|
*	synth-stmts: fix thinko (need to adjust type for indexed a 1-bit array).	Tristan Gingold	2019-10-13	1	-2/+5
\|
*	testsuite/synth: add testcase for previous commit.	Tristan Gingold	2019-10-13	3	-1/+46
\|
*	synth-stmts: handle const indexed array.	Tristan Gingold	2019-10-13	1	-0/+5
\|
*	synth-oper: handle const array array concat.	Tristan Gingold	2019-10-13	1	-16/+41
\|
*	synth-oper: add more operations (float div, less for arrays)	Tristan Gingold	2019-10-13	1	-7/+39
\|
*	testsuite/synth: Add testcase for previous commit (missing assoc in call).	Tristan Gingold	2019-10-13	3	-0/+67
\|
*	synth-stmts: improve support for associations in function calls.	Tristan Gingold	2019-10-13	1	-19/+92
\|
*	synth-inst: minor refactoring.	Tristan Gingold	2019-10-13	1	-3/+2
\|
*	synth-oper: handle unsigned unsigned mul.	Tristan Gingold	2019-10-13	1	-0/+13
\|
*	synth-expr: handle integer type conversion.	Tristan Gingold	2019-10-13	1	-1/+4
\|
*	synth-expr: handle range array attribute in slices.	Tristan Gingold	2019-10-13	1	-42/+74
\|
*	vhdl-annotations: handle list of record elements declaration.	Tristan Gingold	2019-10-13	1	-2/+4
\|
*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	4	-20/+31
\| \| \| \|	Handle more operators in synth.
*	netlists-iterators: avoid a crash if no ports.	Tristan Gingold	2019-10-13	1	-3/+1
\|
*	netlists-dump: improve output.	Tristan Gingold	2019-10-13	1	-9/+28
\|
*	netlists-builders: adjust names of dyn_extract ports.	Tristan Gingold	2019-10-13	1	-2/+2
\|
*	Show error on wait without condition (#976)	Pepijn de Vos	2019-10-13	1	-0/+4
\| \| \| \| \| \|	* Show error on wait without condition * Null node
*	add record (in)equality (#975)	Pepijn de Vos	2019-10-13	1	-2/+4
\|
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	7	-195/+218
\|
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	9	-24/+85
\|
*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	4	-23/+44
\|
*	vhdl: do not try to recognize mentor version of std_logic_arith.	Tristan Gingold	2019-10-10	1	-0/+7
\|
*	synth: remove synth-types	Tristan Gingold	2019-10-10	4	-91/+13
\|
*	netlists: add internings child package.	Tristan Gingold	2019-10-10	3	-14/+61
\|
*	ghdlsynth: add --out=none to not display the result.	Tristan Gingold	2019-10-10	1	-1/+6
\|
*	netlists-disp_vhdl: fix pasto on id_asr.	Tristan Gingold	2019-10-10	1	-5/+5
\|