| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | simul: handle empty procedures | Tristan Gingold | 2022-09-25 | 1 | -1/+9 |
| * | synth: rework association conversions | Tristan Gingold | 2022-09-25 | 3 | -62/+75 |
| * | synth-vhdl_stmts: rework for subprogram associations (WIP) | Tristan Gingold | 2022-09-25 | 1 | -57/+36 |
| * | synth-vhdl_stmts: support of individual paramater associations (WIP) | Tristan Gingold | 2022-09-25 | 2 | -106/+238 |
| * | simul: reuse drivers extraction from elaboration | Tristan Gingold | 2022-09-25 | 2 | -74/+26 |
| * | synth-vhdl_stmts: refactore synth_subprogram_associations | Tristan Gingold | 2022-09-25 | 1 | -49/+52 |
| * | suite_driver.sh: print a message in case of failure | Tristan Gingold | 2022-09-25 | 1 | -0/+1 |
| * | synth-vhdl_stmts: refactore | Tristan Gingold | 2022-09-25 | 1 | -23/+32 |
| * | synth-vhdl_stmts: refactoring | Tristan Gingold | 2022-09-25 | 1 | -189/+208 |
| * | synth-vhdl_stmts: rework in progress of subprogram associations | Tristan Gingold | 2022-09-25 | 1 | -108/+115 |
| * | pyGHDL: added missing type annotations. Fix #2192 (#2195) | fhuemer | 2022-09-23 | 1 | -2/+2 |
| * | synth-vhdl_insts: move pragma unreferenced | Tristan Gingold | 2022-09-21 | 1 | -1/+2 |
| * | configure: tentatively enable llvm 15 | Tristan Gingold | 2022-09-21 | 1 | -0/+1 |
| * | synth: simplify elab-vhdl_annotations | Tristan Gingold | 2022-09-19 | 2 | -51/+3 |
| * | synth: simplify elab-vhdl_annotations | Tristan Gingold | 2022-09-19 | 5 | -197/+31 |
| * | synth: rename vhdl.annotations to elab.vhdl_annotations | Tristan Gingold | 2022-09-19 | 8 | -18/+20 |
| * | synth: rework subprogram associations (WIP) | Tristan Gingold | 2022-09-19 | 3 | -42/+87 |
| * | synth-vhdl_stmts: minor renaming | Tristan Gingold | 2022-09-18 | 4 | -12/+12 |
| * | synth: fix assert failure on attribute specification | Tristan Gingold | 2022-09-18 | 1 | -1/+5 |
| * | simul: handle individual port associations with expressions | Tristan Gingold | 2022-09-18 | 1 | -1/+5 |
| * | simul: handle type conversions in port associations | Tristan Gingold | 2022-09-18 | 3 | -49/+57 |
| * | synth: handle open variable association | Tristan Gingold | 2022-09-17 | 1 | -22/+31 |
| * | simul: fix resolved association | Tristan Gingold | 2022-09-17 | 2 | -2/+3 |
| * | simul: use synth_declarations for processes and procedures | Tristan Gingold | 2022-09-17 | 4 | -18/+15 |
| * | synth: factorize code (reuse synth_constant_declaration) | Tristan Gingold | 2022-09-17 | 8 | -71/+22 |
| * | synth: handle protected types in subprograms | Tristan Gingold | 2022-09-17 | 3 | -38/+53 |
| * | synth: improve file handling (skip extra data, errors) | Tristan Gingold | 2022-09-17 | 3 | -3/+53 |
| * | synth: finalize files | Tristan Gingold | 2022-09-17 | 3 | -4/+30 |
| * | synth: handle read length on text files | Tristan Gingold | 2022-09-17 | 1 | -16/+40 |
| * | synth: handle incomplete types | Tristan Gingold | 2022-09-17 | 6 | -24/+87 |
| * | synth: handle individual generic associations | Tristan Gingold | 2022-09-17 | 1 | -5/+35 |
| * | synth: factorize code with synth_assignment_prefix | Tristan Gingold | 2022-09-16 | 1 | -75/+15 |
| * | synth: preliminary work to factorize code | Tristan Gingold | 2022-09-16 | 6 | -52/+69 |
| * | simul: handle active attribute | Tristan Gingold | 2022-09-16 | 4 | -11/+58 |
| * | synth: handle val attribute for static bit/logic values | Tristan Gingold | 2022-09-16 | 1 | -0/+3 |
| * | simul: improve support of concurrent procedure call | Tristan Gingold | 2022-09-16 | 1 | -1/+20 |
| * | simul: improve error handling during elaboration | Tristan Gingold | 2022-09-16 | 2 | -5/+6 |
| * | synth: improve handling of complex types | Tristan Gingold | 2022-09-15 | 4 | -8/+30 |
| * | synth: handle vhdl-87 files | Tristan Gingold | 2022-09-15 | 2 | -2/+14 |
| * | synth: handle access subtypes | Tristan Gingold | 2022-09-15 | 2 | -1/+9 |
| * | synth: handle read for files of unconstrained arrays | Tristan Gingold | 2022-09-15 | 3 | -1/+54 |
| * | simul: handle more signals types | Tristan Gingold | 2022-09-15 | 2 | -23/+128 |
| * | testsuite/gna: add a test for #2189 | Tristan Gingold | 2022-09-15 | 4 | -0/+69 |
| * | trans-chap7: fix choice of exp. Fix #2189 | Tristan Gingold | 2022-09-15 | 1 | -3/+3 |
| * | ortho/mcode: add reg move for ret. Fix #2189 | Tristan Gingold | 2022-09-15 | 2 | -7/+17 |
| * | synth-vhdl_stmts: handle attribute names in expressions | Tristan Gingold | 2022-09-14 | 1 | -1/+3 |
| * | simul: handle --expect-failure for elaboration | Tristan Gingold | 2022-09-14 | 3 | -11/+15 |
| * | synth: detect overflow in static exponentiation | Tristan Gingold | 2022-09-14 | 6 | -76/+266 |
| * | synth: add bounds check for float-integer type conversion | Tristan Gingold | 2022-09-12 | 1 | -2/+21 |
| * | simul: factorize code for conversion functions | Tristan Gingold | 2022-09-12 | 1 | -19/+6 |
