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* grt: Use GRTs sort for dump table.Ondrej Ille2021-04-221-9/+19
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* grt-avls: optimize, disable debug check after insertMartin Jeřábek2021-04-221-4/+4
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* grt: optimize wave dumpMartin Jeřábek2021-04-224-11/+49
| | | | | | | | Instead of walking through all the signals every cycle, keep an array of changed signals (without duplicates). Before dumping, sort the array. Afterwards clear it. This massively improves performance on big designs.
* doc/using: document command 'elab-order' (79fc4b05)umarcor2021-04-221-0/+18
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* doc: style, use 'file...' consistentlyumarcor2021-04-222-2/+2
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* doc: style, use '[options...]' consistentlyumarcor2021-04-222-13/+13
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* doc/synth: clarify that we need '-e' for resolving the ambiguity between a ↵umarcor2021-04-221-13/+21
| | | | unit name and a filename
* doc: add/rename '[library.]top_unit [arch]', style (849a25e0)umarcor2021-04-223-299/+371
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* doc: pin sphinx to v3.3.1 to prevent search bugumarcor2021-04-221-1/+1
| | | | | | | | | | Search is broken with >=3.3.1 (VUnit/vunit#713). We use the same template in VUnit and here, which is based on sphinx_rtd_theme. Moreover, sphinx_rtd_theme is broken with docutils>=0.16 (see readthedocs/sphinx_rtd_theme#1115). So, we are temporarily pinning those (see buildthedocs/docker@f7bda0e and buildthedocs/docker@1fd9555) until sphinx_rtd_theme is either fixed or updated (they are expecting to deprecate the current theme and use a new one based on bootstrap, see readthedocs/sphinx_rtd_theme#1086). Then, we will either rebase or update buildthedocs/sphinx.theme for picking the fixes.
* testsuite/synth: add a test for #1731Tristan Gingold2021-04-212-0/+24
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* synth-vhdl_oper.adb: handle resize uns/uns. For #1731Tristan Gingold2021-04-211-0/+12
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* synth-vhdl_oper.adb: adjust previous patch and testTristan Gingold2021-04-212-2/+17
| | | | | resize with two signed parameters extract the size of the second parameter to resize the first one.
* testsuite/synth: add a test for #1731Tristan Gingold2021-04-213-0/+221
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* synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731Tristan Gingold2021-04-211-0/+1
| | | | With an hint from T.Meissner
* synth: extract synth-memtype from synth-objtypesTristan Gingold2021-04-2115-124/+193
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* Revert changing parameter types of Get-VHDLVariables functionMartin Bahlinger2021-04-201-2/+2
| | | | This change from commit 9c4c05cc led to "positional parameter cannot be found" error with PS 5.1
* Move --std= parameter before -frelaxed-rulesMartin Bahlinger2021-04-207-10/+10
| | | | This is required for script to work also with ghdl > 0.37 and --std=08
* VHPI: improve C enum interopMarlon James2021-04-193-66/+113
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* VHPI: add tracing testsMarlon James2021-04-1810-4/+154
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* VHPI: add tracingMarlon James2021-04-182-141/+706
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* Update license headerMarlon James2021-04-182-36/+19
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* testsuite/gna: add a test for #1726Tristan Gingold2021-04-173-0/+47
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* vhdl: handle object interface using an interface type. Fix #1726Tristan Gingold2021-04-173-4/+56
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* testsuite/gna: add a test for #1727Tristan Gingold2021-04-162-0/+24
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* vhdl-sem_names: avoid a crash for invalid user attribute prefix. Fix #1727Tristan Gingold2021-04-161-1/+2
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* synth: renaming (synth-heap -> synth-vhdl_heap)Tristan Gingold2021-04-165-11/+11
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* synth: renaming (synth-static_proc -> synth-vhdl_static_proc)Tristan Gingold2021-04-163-6/+6
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* synth: refactoring (synth.files_operations -> synth.vhdl_files)Tristan Gingold2021-04-166-11/+11
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* synth: renaming (synth.oper -> synth.vhdl_oper)Tristan Gingold2021-04-164-11/+11
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* synth: refactoring (synth.aggr -> synth.vhdl_aggr)Tristan Gingold2021-04-163-7/+7
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* synth: rename synth-context to synth-vhdl_contextTristan Gingold2021-04-1616-25/+25
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* testsuite/gna: add a test for #1724Tristan Gingold2021-04-152-0/+11
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* vhdl: also allow type and subtype declarations in vunit. For #1724Tristan Gingold2021-04-152-0/+4
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* testsuite/synth: add a test for previous commitTristan Gingold2021-04-152-0/+72
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* synth: avoid crash in case of non-elaboratable generic.Tristan Gingold2021-04-152-4/+10
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* vhdl-canon_psl: handle imp_boolTristan Gingold2021-04-151-2/+3
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* testsuite/gna: add test for #1724Tristan Gingold2021-04-153-0/+33
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* vhdl: handle constant declarations in PSL vunit. Fix #1724Tristan Gingold2021-04-152-0/+2
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* testsuite/gna: add tests for #1721Tristan Gingold2021-04-133-0/+43
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* testsuite/gna: add a test for #1721Tristan Gingold2021-04-132-0/+22
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* trans-chap9: handle N_Imp_Bool for PSL. For #1721Tristan Gingold2021-04-131-0/+21
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* testsuite/gna: add a test for #1721Tristan Gingold2021-04-132-0/+29
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* psl: suffix implication are properties (for simple subset). For #1721Tristan Gingold2021-04-133-6/+5
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* testsuite/gna: add a test for #1721Tristan Gingold2021-04-133-0/+80
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* vhdl-sem_psl.adb: can also extract clock from SERE. For #1721Tristan Gingold2021-04-131-1/+5
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* testsuite/gna: add a test for #1717Tristan Gingold2021-04-112-0/+60
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* vhdl-sem_names.adb: fix check for object prefix of subtype attribute. Fix #1717Tristan Gingold2021-04-111-3/+1
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* src: Clarify error for conditional signal assignment.Ondrej Ille2021-04-111-1/+2
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* src: Allow case generate only in VHDL 2008.Ondrej Ille2021-04-111-0/+1
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* src: Unify check for VHDL at least 2008Ondrej Ille2021-04-111-47/+25
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