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* testsuite/synth: add a test for #1850Tristan Gingold2021-08-273-0/+82
* vhdl-parse: support for-generate in vunits. Fix #1850Tristan Gingold2021-08-271-2/+10
* testsuite/synth: Add a test for ghdl/ghdl-yosys-plugin#154Tristan Gingold2021-08-272-0/+58
* synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
* std_names: add name keep.Tristan Gingold2021-08-273-183/+186
* netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
* ghdlsynth.adb: fix a typoTristan Gingold2021-08-261-1/+1
* testsuite/gna: add a test for #1832Tristan Gingold2021-08-262-0/+132
* PSL: handle inf in star repeat sequence. Fix #1832Tristan Gingold2021-08-269-11/+44
* testsuite/gna: add a reproducer for #1834Tristan Gingold2021-08-263-0/+59
* vhdl-evaluation: check integer evaluations fit in base type. Fix #1834Tristan Gingold2021-08-262-11/+37
* testsuite/synth: add a test for #1838Tristan Gingold2021-08-252-0/+48
* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-255-20/+34
* ortho/gcc: adjust and propagate to all gcc versions the change for #1845Tristan Gingold2021-08-256-1/+81
* testsuite/gna: add a testcase for #1844Tristan Gingold2021-08-252-0/+56
* vhdl-sem_types.adb: refine conditions for resolution functions.Tristan Gingold2021-08-251-3/+7
* ghdldrv: handle auxbase option in ortho/gcc. Fix #1845Tristan Gingold2021-08-242-10/+16
* testsuite/gna: add a test for #1814Tristan Gingold2021-08-243-0/+72
* testsuite/gna: add a test for #1837Tristan Gingold2021-08-242-0/+19
* vhdl-parse.adb: improve error recovery. For #1837Tristan Gingold2021-08-241-0/+2
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-2423-643/+377
* vhdl-sem_specs: avoid ownership issue on default map aspect.Tristan Gingold2021-08-241-1/+4
* Changed Debian 'Buster' to 'Bullseye'Patrick Lehmann2021-08-233-3/+3
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| * Debian Bullseye was releasedumarcor2021-08-233-3/+3
* | Set black formatting to 120 chars per line.Patrick Lehmann2021-08-2333-757/+234
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| * pyGHDL/lsp: styleumarcor2021-08-231-6/+3
| * black: rerun, to pick pyproject settingsumarcor2021-08-2332-754/+232
| * add pyproject.tomlumarcor2021-08-231-0/+2
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* pyGHDL: update to pyVHDLModel v0.11.5 (#1822)Unai Martinez-Corral2021-08-2329-913/+3376
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| * Skip null statement.Patrick Lehmann2021-08-232-1/+8
| * Fixes due to a bug in pyVHDLModel. Name Context was used twice.Patrick Lehmann2021-08-2311-100/+108
| * Some fixes.Patrick Lehmann2021-08-235-21/+21
| * ci: styleumarcor2021-08-231-8/+21
| * Fixed case statement.Patrick Lehmann2021-08-232-7/+3
| * Handle subprogram vs. subprogram body.Patrick Lehmann2021-08-231-7/+45
| * Handle open in map aspects.Patrick Lehmann2021-08-233-1/+20
| * Assertion messages are optional in assert statements.Patrick Lehmann2021-08-231-2/+7
| * Also handle parameters for sequential procedure calls.Patrick Lehmann2021-08-231-7/+6
| * Handle associations.Patrick Lehmann2021-08-234-32/+177
| * Handle simple sequential signal assignments and it's waveforms.Patrick Lehmann2021-08-233-17/+26
| * Implemented handling of wait statements.Patrick Lehmann2021-08-233-12/+61
| * Read condition, message and severity from asserts and reports.Patrick Lehmann2021-08-232-17/+22
| * Some updates.Patrick Lehmann2021-08-234-21/+75
| * Fixed pretty printer after model fix.Patrick Lehmann2021-08-231-1/+1
| * Handle context references.Patrick Lehmann2021-08-233-11/+35
| * Handle contexts.Patrick Lehmann2021-08-237-39/+118
| * Implemented if, case and for-loop statements.Patrick Lehmann2021-08-234-63/+88
| * Handle if-statements.Patrick Lehmann2021-08-232-14/+9
| * Extended testcase.Patrick Lehmann2021-08-231-1/+9
| * Handle bodies in case generate statements.Patrick Lehmann2021-08-232-25/+30
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