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* synth: add Id_Port gate to improve display.Tristan Gingold2019-07-105-29/+73
* synth: display instances in reverse order.Tristan Gingold2019-07-102-10/+41
* synth: handle instantiation (WIP)Tristan Gingold2019-07-1011-48/+587
* vhdl: improve an error message.Tristan Gingold2019-07-101-1/+1
* Add synth testsuite to CI (#862)1138-4EB2019-07-105-34/+71
* vhdl-sem_lib: Load_Parse_Design_Unit: ignore checksum ifTristan Gingold2019-07-091-3/+6
* vhdl-sem_lib: free_dependencies: only free entity aspect.Tristan Gingold2019-07-091-3/+19
* libghdl: automatically set the prefix from shared libraryTristan Gingold2019-07-094-13/+26
* fix: *gcc* build and run docker images are now named *gcc (#865)1138-4EB2019-07-091-9/+18
* doc: update list of supported LLVM versions (#863)1138-4EB2019-07-092-8/+2
* Add a test for ghdl/ghdl-language-server#7Tristan Gingold2019-07-093-2/+10
* ghdllocal: correctly disp GHDL_PREFIX in --disp-config.Tristan Gingold2019-07-093-8/+8
* Add testcase for #864Tristan Gingold2019-07-093-0/+90
* vhdl: report an error in case of missing binding indication in config spec.Tristan Gingold2019-07-091-11/+21
* python: add errorout_console, disp_config.Tristan Gingold2019-07-082-0/+6
* Fix a merge collision.Tristan Gingold2019-07-081-154/+84
* synthesis: add Node instead of Iir.Tristan Gingold2019-07-081-10/+10
* vhdl simul-elaboration: minor rewrite.Tristan Gingold2019-07-081-3/+1
* synth-environement: add comments.Tristan Gingold2019-07-082-3/+5
* Add testcase for #860Tristan Gingold2019-07-082-0/+68
* add info about the structure of the project (#861)1138-4EB2019-07-073-16/+59
* synth: handle simple user function calls.Tristan Gingold2019-07-066-18/+89
* synth: support top-level generics.Tristan Gingold2019-07-062-0/+23
* configure: add --enable-synth (off by default).Tristan Gingold2019-07-066-7/+44
* ghdlsynth.h: follow convention, add comments.Tristan Gingold2019-07-041-13/+16
* vhdl-annotations: partial revert of previous patch forTristan Gingold2019-07-042-1/+12
* synth: use future states for PSL restrict directive.Tristan Gingold2019-07-041-5/+8
* synth: handle some "/=".Tristan Gingold2019-07-042-0/+23
* libghdlsynth: catch all exceptions.Tristan Gingold2019-07-041-0/+3
* vhdl/translate: reindent.Tristan Gingold2019-07-041-1/+1
* synth: handle PSL restrict directive (WIP).Tristan Gingold2019-07-042-1/+111
* synth: add concat_array function.Tristan Gingold2019-07-042-36/+52
* netlists-disp_vhdl: display initial value of idff.Tristan Gingold2019-07-041-19/+32
* netlists: export new_internal_name.Tristan Gingold2019-07-041-4/+10
* netlists: allow to build idff without a connected D.Tristan Gingold2019-07-042-3/+6
* netlists: add reduce_or/reduce_and gates.Tristan Gingold2019-07-044-0/+36
* netlists: add assume gate.Tristan Gingold2019-07-045-3/+29
* libghdlsynth: decode options.Tristan Gingold2019-07-043-76/+104
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-0418-60/+60
* parse: improve error message for incorrect use of '!'.Tristan Gingold2019-07-041-0/+4
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-0420-130/+357
* Move pnodes.py.py to xtools directory.Tristan Gingold2019-07-042-4/+1
* synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.Tristan Gingold2019-07-045-17/+30
* synth: emit an error for non-constant bounds.Tristan Gingold2019-07-041-0/+4
* synth: ignore non object aliases.Tristan Gingold2019-07-031-0/+2
* Add test for previous commit.Tristan Gingold2019-07-032-0/+38
* vhdl: translate anonymous_signal_declaration.Tristan Gingold2019-07-034-9/+8
* testsuite: add a case for previous commit.Tristan Gingold2019-07-032-0/+47
* vhdl: avoid a crash on label parenthesis.Tristan Gingold2019-07-031-0/+1
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-0320-526/+785
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