iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Makefile.in: install synth include files as part of libghdl.	Tristan Gingold	2019-08-15	1	-1/+6
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*	configure: complete --help	Tristan Gingold	2019-08-15	1	-0/+2
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*	testsuite/synth: fix assert1 assertion.	Tristan Gingold	2019-08-15	1	-1/+1
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*	add synthesis support for logic operators on numeric types (#893)	Pepijn de Vos	2019-08-15	5	-7/+152
\| \| \| \| \| \| \| \|	* add logic operators on unsigned * handle signed too * handle unary not
*	synth: fix handling of assume/assert.	Tristan Gingold	2019-08-14	1	-6/+65
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*	ghdlsynth: add command to get libghdl paths.	Tristan Gingold	2019-08-14	4	-22/+97
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*	ghdldrv: move command_str_disp from ghdlvpi to ghdlmain	Tristan Gingold	2019-08-14	3	-38/+38
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*	testenv: also applies GHDL_FLAGS for synth.	Tristan Gingold	2019-08-14	1	-1/+1
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*	ghdlsynth: declare init_for_ghdl_synth.	Tristan Gingold	2019-08-14	1	-1/+4
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*	update NEWS.md. Fix #891	Tristan Gingold	2019-08-14	1	-1/+8
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*	synth: add test for previous commit.	Tristan Gingold	2019-08-14	3	-2/+29
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*	vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.	Tristan Gingold	2019-08-14	2	-0/+12
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*	vhdl: add PSL keywords to vhdl08 reserved words.	Tristan Gingold	2019-08-14	10	-242/+257
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*	testsuite/gna: use common testsuite.sh	Tristan Gingold	2019-08-14	1	-14/+5
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*	testsuite/gna/README: document naming convention.	Tristan Gingold	2019-08-14	1	-2/+11
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*	testsuite/gna: make testsuite.py neutral.	Tristan Gingold	2019-08-14	1	-4/+1
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*	testsuite/gna: rename perf02 to not run it normally.	Tristan Gingold	2019-08-14	36	-0/+0
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*	testsuite/synth: make testsuite.sh more neutral.	Tristan Gingold	2019-08-14	1	-2/+2
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*	testsuite/testenv.sh: define PYTHON	Tristan Gingold	2019-08-14	1	-0/+2
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*	testsuite/python: add testsuite.sh	Tristan Gingold	2019-08-14	1	-0/+53
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*	testsuite: add testsuite.sh in 001units	Tristan Gingold	2019-08-14	1	-0/+7
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*	Fix build of upf packages for openieee.	Tristan Gingold	2019-08-14	1	-5/+5
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*	synth: also extract edge in PSL expressions.	Tristan Gingold	2019-08-13	5	-19/+64
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*	synth: extract edge for PSL clocks.	Tristan Gingold	2019-08-13	5	-29/+120
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*	vhdl-nodes_walk: handle iir_kind_psl_default_clock.	Tristan Gingold	2019-08-13	1	-1/+2
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*	libghdlsynth: make it almost empty, as libghdl will be used instead.	Tristan Gingold	2019-08-13	1	-8/+0
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*	Support for PSL assert and assume in synthesis (#892)	Pepijn de Vos	2019-08-13	2	-5/+55
\| \| \| \| \| \| \| \|	* initial support for PSL assert and assume * add support for true, false, and, or in psl synth * update testsuite with new psl things
*	libghdl: also add synthesis part. For #884	Tristan Gingold	2019-08-13	7	-55/+61
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*	synth: build_header was replaced by a Makefile target.	Tristan Gingold	2019-08-13	1	-8/+0
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*	libghdl: preliminary work to also support synth.	Tristan Gingold	2019-08-13	3	-4/+10
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*	openieee: add dummy UPF package (#889)	1138-4EB	2019-08-11	3	-1/+47
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*	vhdl: improve reprint of inertial association.	Tristan Gingold	2019-08-11	6	-181/+206
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*	Add testcase for #885	Tristan Gingold	2019-08-11	2	-0/+44
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*	vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.	Tristan Gingold	2019-08-11	1	-1/+24
\| \| \| \|	Fix #885
*	Add testcase for #886	Tristan Gingold	2019-08-10	5	-0/+141
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*	vhdl: avoid crash on incorrect unit name.	Tristan Gingold	2019-08-10	2	-6/+36
\| \| \| \|	Fix #886
*	vhdl: handle subtype indication (with range) in discrete_range.	Tristan Gingold	2019-08-10	7	-63/+105
\| \| \| \|	For #877
*	synth: add comments.	Tristan Gingold	2019-08-09	1	-1/+9
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*	vhdl: remove unused Get/Set_Choice_Order.	Tristan Gingold	2019-08-09	7	-580/+515
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*	synth: add testcase from #872	Tristan Gingold	2019-08-08	2	-0/+51
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*	synth: add testcase for aggregate target.	Tristan Gingold	2019-08-08	3	-0/+56
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*	synth: fix crash when assignment target is an aggregate.	Tristan Gingold	2019-08-08	1	-5/+7
\| \| \| \|	For tgingold/ghdlsynth-beta#26
*	vhdl: remove -Whides warnings for processes without a label.	Tristan Gingold	2019-08-08	1	-0/+9
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*	Add reproducer for tgingold/ghdlsynth-beta#26	Tristan Gingold	2019-08-08	2	-0/+29
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*	synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.	Tristan Gingold	2019-08-08	2	-4/+13
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*	vhdl: remove severity from cover, report and severity from assume.	Tristan Gingold	2019-08-08	11	-142/+160
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*	pnodes.py: be strict about comments, refactoring.	Tristan Gingold	2019-08-07	1	-42/+62
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*	vhdl-nodes: gather PSL nodes, regenerate nodes_meta.	Tristan Gingold	2019-08-07	2	-125/+91
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*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	36	-251/+555
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	Add testcase for #877	Tristan Gingold	2019-08-06	5	-0/+43
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