2 files changed, 29 insertions, 8 deletions
diff --git a/testsuite/synth/const01/const03.vhdl b/testsuite/synth/const01/const03.vhdl
new file mode 100644
index 000000000..4ffd037f5
--- /dev/null
+++ b/testsuite/synth/const01/const03.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity const03 is
+  port (v : std_logic_vector (15 downto 0);
+        o : out std_logic_vector (3 downto 0));
+end const03;
+
+architecture behav of const03 is
+  function count (vec : std_logic_vector) return std_logic_vector
+  is
+    variable res : std_logic_vector (3 downto 0) := x"0";
+  begin
+    for i in vec'range loop
+      if vec (i) = '1' then
+        res := std_logic_vector (unsigned(res) + 1);
+      end if;
+    end loop;
+    return res;
+  end count;
+begin
+  o <= count(v);
+end behav;
diff --git a/testsuite/synth/const01/testsuite.sh b/testsuite/synth/const01/testsuite.sh
index 1a49d8a5d..e72cffdcd 100755
--- a/testsuite/synth/const01/testsuite.sh
+++ b/testsuite/synth/const01/testsuite.sh
@@ -3,14 +3,11 @@
 . ../../testenv.sh
 
 for t in const01; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t --ieee-asserts=disable-at-0
-    clean
+    synth_tb $t
 done
 
+# synth const02.vhdl -e > syn_const02.vhdl
+synth_analyze const03
+clean
+
 echo "Test successful"