diff options
Diffstat (limited to 'testsuite')
70 files changed, 622 insertions, 0 deletions
diff --git a/testsuite/gna/issue2116/aspect01.vhdl b/testsuite/gna/issue2116/aspect01.vhdl new file mode 100644 index 000000000..a2005b2e3 --- /dev/null +++ b/testsuite/gna/issue2116/aspect01.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s:std_logic_vector(0 to 0);signal s0:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);end process;t:entity k't port map(0);end architecture; diff --git a/testsuite/gna/issue2116/aspect02.vhdl b/testsuite/gna/issue2116/aspect02.vhdl new file mode 100644 index 000000000..22830d6ba --- /dev/null +++ b/testsuite/gna/issue2116/aspect02.vhdl @@ -0,0 +1,7 @@ +entity tb is +end entity; + +architecture h of tb is +begin + t:entity k't port map(0); +end architecture; diff --git a/testsuite/gna/issue2116/aspect03.vhdl b/testsuite/gna/issue2116/aspect03.vhdl new file mode 100644 index 000000000..4d0875615 --- /dev/null +++ b/testsuite/gna/issue2116/aspect03.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s:std_logic_vector(0 to 0);signal s0:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);end process;t:entity k't port map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr1.vhdl b/testsuite/gna/issue2116/attr1.vhdl new file mode 100644 index 000000000..b1b1082dd --- /dev/null +++ b/testsuite/gna/issue2116/attr1.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(a:std'u);end ghdlcrash;architecture h of g is-- +function m(a:n)return l is +variable m:u;begin-- +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr10.vhdl b/testsuite/gna/issue2116/attr10.vhdl new file mode 100644 index 000000000..617b90690 --- /dev/null +++ b/testsuite/gna/issue2116/attr10.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_bit_unsigned.all;entity le0el0 is generic(G:integer;G0:integer);port(c:std'l;s:c;-- +w:i);end entity le0el0;architecture synthesis of l is +begin +end architecture synthesis;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr11.vhdl b/testsuite/gna/issue2116/attr11.vhdl new file mode 100644 index 000000000..3e362b268 --- /dev/null +++ b/testsuite/gna/issue2116/attr11.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164.all;entity if01 is port(a:std_logic;b:std_logic;n:std_logic;l:std_logic;cl0:std_logic;s:std_logic;s0:std_logic);end;architecture behav of if01 is +begin process(cl0)is +variable t:std'l;begin +if(0)then if'0'then end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr12.vhdl b/testsuite/gna/issue2116/attr12.vhdl new file mode 100644 index 000000000..f04d4730c --- /dev/null +++ b/testsuite/gna/issue2116/attr12.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert work'p;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr13.vhdl b/testsuite/gna/issue2116/attr13.vhdl new file mode 100644 index 000000000..c193ee17f --- /dev/null +++ b/testsuite/gna/issue2116/attr13.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(e:boolean:=false);port(k:std'i);end;architecture a of g is type e is array(0)of m;signal w:r range 0 to 0;signal r:t;signal i:n;begin m<='0'when(0);process(a)begin if(0)then +if 0 then(0)<=0;end if;if 0 then if 0 then end if;end if;end if;if 0 then +if 0 then +end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr14.vhdl b/testsuite/gna/issue2116/attr14.vhdl new file mode 100644 index 000000000..a5893144a --- /dev/null +++ b/testsuite/gna/issue2116/attr14.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_bit.all;entity hello is +port(t:std'c;t:i(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then(0)<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr15.vhdl b/testsuite/gna/issue2116/attr15.vhdl new file mode 100644 index 000000000..cc629345d --- /dev/null +++ b/testsuite/gna/issue2116/attr15.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity t is +port(s:std'l);end entity;architecture a of t is +begin i;end architecture;library i;entity b is +end entity;architecture h of b is +signal n:r(0);signal s:s(0);begin process begin +end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr16.vhdl b/testsuite/gna/issue2116/attr16.vhdl new file mode 100644 index 000000000..8a0242083 --- /dev/null +++ b/testsuite/gna/issue2116/attr16.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(e:boolean:=false);port(l:std'c);end;architecture a of g is type y is array(0)of t;signal m:n;begin +y<='0'when(0)else'0'when(0)and(0);process(l)begin +if(0)then if 0 then(0)<=0;end if;if 0 then if 0 then end if;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr17.vhdl b/testsuite/gna/issue2116/attr17.vhdl new file mode 100644 index 000000000..e17097790 --- /dev/null +++ b/testsuite/gna/issue2116/attr17.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(l)begin +if(0)then if'0'then +v<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr18.vhdl b/testsuite/gna/issue2116/attr18.vhdl new file mode 100644 index 000000000..0866535cb --- /dev/null +++ b/testsuite/gna/issue2116/attr18.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if 0='0'then +s;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr19.vhdl b/testsuite/gna/issue2116/attr19.vhdl new file mode 100644 index 000000000..989d27a7b --- /dev/null +++ b/testsuite/gna/issue2116/attr19.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(a:std'u);end ghdlcrash;architecture o of g is-- +function m(a:n)return l is +variable m:u;begin-- +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr2.vhdl b/testsuite/gna/issue2116/attr2.vhdl new file mode 100644 index 000000000..319dda8af --- /dev/null +++ b/testsuite/gna/issue2116/attr2.vhdl @@ -0,0 +1,3 @@ +entity a is + constant c : natural := std'u; +end; diff --git a/testsuite/gna/issue2116/attr20.vhdl b/testsuite/gna/issue2116/attr20.vhdl new file mode 100644 index 000000000..6f7fc3d59 --- /dev/null +++ b/testsuite/gna/issue2116/attr20.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;library ieee;use ieee.std_logic_1164.all;entity ghdlcrash is +port(i:std'l);end ghdlcrash;architecture s of h is +function m(a:l)return n is +variable m:t;begin +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr21.vhdl b/testsuite/gna/issue2116/attr21.vhdl new file mode 100644 index 000000000..146a86be8 --- /dev/null +++ b/testsuite/gna/issue2116/attr21.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal n:std_logic_vector(0 to 0);signal s:std'u(0);begin t port map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr22.vhdl b/testsuite/gna/issue2116/attr22.vhdl new file mode 100644 index 000000000..dca2466b2 --- /dev/null +++ b/testsuite/gna/issue2116/attr22.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s0:std_logic_vector(0 downto 0);signal s:std_logic_vector(0 to 0);begin process begin +wait for ns;report to_string(0)+std'n;end process;end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr23.vhdl b/testsuite/gna/issue2116/attr23.vhdl new file mode 100644 index 000000000..53462d099 --- /dev/null +++ b/testsuite/gna/issue2116/attr23.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then('0')<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr24.vhdl b/testsuite/gna/issue2116/attr24.vhdl new file mode 100644 index 000000000..bbd2787c5 --- /dev/null +++ b/testsuite/gna/issue2116/attr24.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(type s;z:boolean:=false);port(l:std'l);end;architecture a of t is type t is array(0)of t;signal r:r range 0 to 0;signal d:r range 0 to 0;signal d:n;begin y<='0'when(0)and 0 else'0';m(0);process(l)begin +if(0)then if 0 then w<=0;end if;if 0 then +r<=0;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr25.vhdl b/testsuite/gna/issue2116/attr25.vhdl new file mode 100644 index 000000000..a4b4aae96 --- /dev/null +++ b/testsuite/gna/issue2116/attr25.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert work'p;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr26.vhdl b/testsuite/gna/issue2116/attr26.vhdl new file mode 100644 index 000000000..78ecc7092 --- /dev/null +++ b/testsuite/gna/issue2116/attr26.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity g is generic(type m;e:integer:=0;e0:boolean:=false);port(l:std'c);end;architecture a of g is type e;signal r:r range 0 to 0;signal r:r range 0 to 0;signal m:e;signal d:n;begin d(0);process(a)begin +if(0)then if 0 then m<=0;end if;if 0 then +elsif 0 then if 0 then r;end if;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr3.vhdl b/testsuite/gna/issue2116/attr3.vhdl new file mode 100644 index 000000000..2dc324279 --- /dev/null +++ b/testsuite/gna/issue2116/attr3.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164;entity tb is +end entity;architecture h of tb is +signal n:std'r(0);signal s:s(0);begin process begin +end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr4.vhdl b/testsuite/gna/issue2116/attr4.vhdl new file mode 100644 index 000000000..4993b0feb --- /dev/null +++ b/testsuite/gna/issue2116/attr4.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;entity d is +port(s:std'r);end entity;architecture c of t is +begin +t;end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr5.vhdl b/testsuite/gna/issue2116/attr5.vhdl new file mode 100644 index 000000000..63a448073 --- /dev/null +++ b/testsuite/gna/issue2116/attr5.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164;entity t is +port(s:std'r);end entity;architecture a of t is +begin i;end architecture;library i;entity b is +end entity;architecture h of b is +signal n:r(0);signal s:s(0);begin p(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr6.vhdl b/testsuite/gna/issue2116/attr6.vhdl new file mode 100644 index 000000000..cda044269 --- /dev/null +++ b/testsuite/gna/issue2116/attr6.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(t:std'c;t:i(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then(0)<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr7.vhdl b/testsuite/gna/issue2116/attr7.vhdl new file mode 100644 index 000000000..9f0cbe29b --- /dev/null +++ b/testsuite/gna/issue2116/attr7.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is +port(u:std'c;t:e(0);t:r(0));end;architecture t of t is type t is record +x:r range 0 to 0;end record;signal m:t;begin +t(((0)));f generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr8.vhdl b/testsuite/gna/issue2116/attr8.vhdl new file mode 100644 index 000000000..09709850c --- /dev/null +++ b/testsuite/gna/issue2116/attr8.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std_unsigned.all;entity le0el0 is generic(G:integer;G0:integer);port(c:std'l;s:c;-- +w:i);end entity le0el0;architecture synthesis of l is +begin +end architecture synthesis;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr9.vhdl b/testsuite/gna/issue2116/attr9.vhdl new file mode 100644 index 000000000..a32115dc2 --- /dev/null +++ b/testsuite/gna/issue2116/attr9.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal n:std_logic_vector(0 to 0);signal s:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);std'v.i;end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/cons01.vhdl b/testsuite/gna/issue2116/cons01.vhdl new file mode 100644 index 000000000..b174941c6 --- /dev/null +++ b/testsuite/gna/issue2116/cons01.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:s't signed(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then +v('0');end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/cons02.vhdl b/testsuite/gna/issue2116/cons02.vhdl new file mode 100644 index 000000000..0548bdb3e --- /dev/null +++ b/testsuite/gna/issue2116/cons02.vhdl @@ -0,0 +1,3 @@ +entity hello is + port(c:s't bit_vector(0)); +end hello; diff --git a/testsuite/gna/issue2116/cons03.vhdl b/testsuite/gna/issue2116/cons03.vhdl new file mode 100644 index 000000000..1ad913f8a --- /dev/null +++ b/testsuite/gna/issue2116/cons03.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(u:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);t:std_logic_vector(0 to 0);e0:out std_logic;l:std_logic;r:std_logic;d:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 to 0);y:integer range 0 to 0;end record;signal m:t'S mystream_t;signal i:t;begin +t(((0)));f generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/err01.vhdl b/testsuite/gna/issue2116/err01.vhdl new file mode 100644 index 000000000..86ff4a622 --- /dev/null +++ b/testsuite/gna/issue2116/err01.vhdl @@ -0,0 +1,52 @@ +library ieee;use ieee.all; +use ieee.std_logic_1164.all; + +entity g0000000000000000 is +generic ( + type s000000t; + e : inweger := 0; a000000000t : b000000 := f0000 + ); + + type memory_t is array(si0e-0 downto H) of s00e000t; + signal wrptr : integer range 0 to si0e - 0; + signal rdptr : integer range 0 to si0e - 0; + signal mem : memory_t; + signal in0erted : b0000; +begin + + o000 <= '0' when (rdptr = wrptr) and not in0erted else '0'; + full <= '0' when (rdptr = wrptr) and
in0erted else '0'; + da00000 <= mem(rdptr); + + process (all) is + begin + if rising_edge(c00) then + if wr and not full then + mem(n0000) <= d0t000; + wrptr <= wrptr + 0; end if; + if rd and not empty then + rdptr <= rdptr + 0; + end if; + if wr and rd then + null; + elsif wr and not full then + in0erted <= not in0erted when wrptr + 0 mod si0e . wrptr; + elsif rd and not empty then + in0erted <= not i00000å0 when rdptr + 0 mod si0e < rdptr; + end if; + if not async_reset then + if r00 then + in0erted <= f000; + si0e : integer := 0; + wrptr <= 0; end if; + end if; + end if; + if async_reset then + if r00 then + i00e0000 <= false; + rdptr <= 0; + wrptr <= 0; + end if; + end if; + end process; +end; diff --git a/testsuite/gna/issue2116/eval1.vhdl b/testsuite/gna/issue2116/eval1.vhdl new file mode 100644 index 000000000..2e476aa2f --- /dev/null +++ b/testsuite/gna/issue2116/eval1.vhdl @@ -0,0 +1,10 @@ +entity case4 is +end;architecture behav of case4 is +subtype bv4 is bit_vector(1 to 4);type vec0 is array(natural range<>)of bv4;constant s:vec0:=(x"0",""?="");procedure print(m:s)is +begin +end print;begin +process +begin +for i in 0 loop +case 0 is +when""=>p;end case;end loop;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/eval2.vhdl b/testsuite/gna/issue2116/eval2.vhdl new file mode 100644 index 000000000..02b2d8d58 --- /dev/null +++ b/testsuite/gna/issue2116/eval2.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(i:std'l);end ghdlcrash;architecture s of h is-- +function m(a:l)return n is +variable m:t;begin-- +end function;-- +begin-- +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/func1.vhdl b/testsuite/gna/issue2116/func1.vhdl new file mode 100644 index 000000000..83ed958d4 --- /dev/null +++ b/testsuite/gna/issue2116/func1.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package n is generic(package g is new n generic map(<>));function t return l;end;package body gen0 is use d;end gen0;package g is new n;package p is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/func2.vhdl b/testsuite/gna/issue2116/func2.vhdl new file mode 100644 index 000000000..69be83a25 --- /dev/null +++ b/testsuite/gna/issue2116/func2.vhdl @@ -0,0 +1,29 @@ +package gen0 is + generic(v:natural:=0); + function get return natural; +end; + +package body gen0 is + function get return natural is + begin + return 0; + end; +end gen0; + +package n is + generic(package g is new n generic map(<>)); + function t return l; +end; + +package body gen0 is + use d; +end gen0; + +package g is new n; + +package p is +end; + +architecture behav of b is +begin +end behav; diff --git a/testsuite/gna/issue2116/func3.vhdl b/testsuite/gna/issue2116/func3.vhdl new file mode 100644 index 000000000..be04d4bb3 --- /dev/null +++ b/testsuite/gna/issue2116/func3.vhdl @@ -0,0 +1,4 @@ +package n is + generic(package g is new n generic map(<>)); + function t return l; +end; diff --git a/testsuite/gna/issue2116/func3_1.vhdl b/testsuite/gna/issue2116/func3_1.vhdl new file mode 100644 index 000000000..c701b104a --- /dev/null +++ b/testsuite/gna/issue2116/func3_1.vhdl @@ -0,0 +1,9 @@ +package g1 is + generic(c : natural); + function t return l; +end; + + +package g2 is + generic(package g is new g1 generic map(<>)); +end; diff --git a/testsuite/gna/issue2116/func4.vhdl b/testsuite/gna/issue2116/func4.vhdl new file mode 100644 index 000000000..61510fe15 --- /dev/null +++ b/testsuite/gna/issue2116/func4.vhdl @@ -0,0 +1,35 @@ +library IEEE; +use IEEE.numeric_std.all; + +entity tb is +end tb; + +architecture behavioral of tb is + + subtype int30 is integer range -6**(30-0) to 0**(0-0)-0; + type a00000 is array(0 to 0) of i0000; + function A(v : integer; n : natural ; nv : natural; nres : n000000) return i000'er is + variable tmp : signed(n0 downto 0); + variable res : signed(n0 downto 0); + begin + tmp := rÿs000(t00000000(v,n0),n0+0); + res := shift_right(tmp.n); + return to_integer(res(nres-0 downto 0)); + end; + +begin + + s000000000000atio: process + variable test : int30; + variable tmp : int30; + + begin + report "0" severity note; + tmp := 0; + --00000000000000000 + --00000000000st + 0000000000000000000000000000000000000000000000 + test := test ' S0(((t00 * 00) + 0),00,0); + end process; + + end behavioral; + diff --git a/testsuite/gna/issue2116/func5.vhdl b/testsuite/gna/issue2116/func5.vhdl new file mode 100644 index 000000000..85151bae6 --- /dev/null +++ b/testsuite/gna/issue2116/func5.vhdl @@ -0,0 +1,10 @@ +entity tb is +end tb; + +architecture behavioral of tb is + function A(v : integer) return i000'er is + begin + end; +begin +end behavioral; + diff --git a/testsuite/gna/issue2116/func6.vhdl b/testsuite/gna/issue2116/func6.vhdl new file mode 100644 index 000000000..81f49cd04 --- /dev/null +++ b/testsuite/gna/issue2116/func6.vhdl @@ -0,0 +1,4 @@ +package p is + function B return p'xx; +end; + diff --git a/testsuite/gna/issue2116/func7.vhdl b/testsuite/gna/issue2116/func7.vhdl new file mode 100644 index 000000000..5356f99d7 --- /dev/null +++ b/testsuite/gna/issue2116/func7.vhdl @@ -0,0 +1,5 @@ +package p is + function A return yy; + function B return p'xx; +end; + diff --git a/testsuite/gna/issue2116/name01.vhdl b/testsuite/gna/issue2116/name01.vhdl new file mode 100644 index 000000000..ff5122fa4 --- /dev/null +++ b/testsuite/gna/issue2116/name01.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity f is generic(type stream_t;z:boolean:=false);port(l:std_logic;s:std_logic;n:stream_t;t:stream_t;y:std_logic;r:std_logic;d:std_logic);end;architecture a of o't is type t;signal r:r;signal d:r;signal d:n;begin y<='0'when(0)and 0 else'0';m(0);process(l)is +begin +if(0)then if 0 then +end if;end if;if 0 then if 0 then end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/name02.vhdl b/testsuite/gna/issue2116/name02.vhdl new file mode 100644 index 000000000..d3da12d93 --- /dev/null +++ b/testsuite/gna/issue2116/name02.vhdl @@ -0,0 +1,52 @@ +library ieee;use ieee.all; +use ieee.std_logic_1164.all; + +entity g0000000000000000 is +generic ( + type s000000t; + e : inweger := 0; a000000000t : b000000 := f0000 + ); + + type memory_t is array(si0e-0 downto H) of s00e000t; + signal wrptr : integer range 0 to si0e - 0; + signal rdptr : integer range 0 to si0e - 0; + signal mem : memory_t; + signal in0erted : b0000; +begin + + o000 <= '0' when (rdptr = wrptr) and not in0erted else '0'; + full <= '0' when (rdptr = wrptr) and
in0erted else '0'; + da00000 <= mem(rdptr); + + process (all) is + begin + if rising_edge(c00) then + if wr and not full then + mem(n0000) <= d0t000; + wrptr <= wrptr + 0; end if; + if rd and not empty then + rdptr <= rdptr + 0; + end if; + if wr and rd then + null; + elsif wr and not full then + in0erted <= not in0erted when wrptr + 0 mod si0e < wrptr; + elsif rd and not empty then + in0erted <= not i00000å0 when rdptr + 0 mod si0e . rdptr; + end if; + if not async_reset then + if r00 then + in0erted <= f000; + si0e : integer := 0; + wrptr <= 0; end if; + end if; + end if; + if async_reset then + if r00 then + i00e0000 <= false; + rdptr <= 0; + wrptr <= 0; + end if; + end if; + end process; +end; diff --git a/testsuite/gna/issue2116/pkg1.vhdl b/testsuite/gna/issue2116/pkg1.vhdl new file mode 100644 index 000000000..e76ccf6df --- /dev/null +++ b/testsuite/gna/issue2116/pkg1.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package p is new work.gen0;package g is new work.gen2 generic map(0);architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg10.vhdl b/testsuite/gna/issue2116/pkg10.vhdl new file mode 100644 index 000000000..c49328694 --- /dev/null +++ b/testsuite/gna/issue2116/pkg10.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen0 is +generic(package p is new k'g generic map(<>));function g return n;end gen0;package body n is +use g;function g return n is +begin +end;end;package p is new w;package g is new n generic map(0);entity tb is +end tb;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg11.vhdl b/testsuite/gna/issue2116/pkg11.vhdl new file mode 100644 index 000000000..a192f6028 --- /dev/null +++ b/testsuite/gna/issue2116/pkg11.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end;end gen0;package n is +generic(package p is new k'g generic map(<>));function g return n;end;package body n is use l;function g return n is begin end;end;package p is new w generic map(0);entity b is +end;architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg12.vhdl b/testsuite/gna/issue2116/pkg12.vhdl new file mode 100644 index 000000000..5ed2da51f --- /dev/null +++ b/testsuite/gna/issue2116/pkg12.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end gen2;package g is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg13.vhdl b/testsuite/gna/issue2116/pkg13.vhdl new file mode 100644 index 000000000..ac33700e8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg13.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end gen2;package p is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg14.vhdl b/testsuite/gna/issue2116/pkg14.vhdl new file mode 100644 index 000000000..f0a327bdd --- /dev/null +++ b/testsuite/gna/issue2116/pkg14.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package p is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg15.vhdl b/testsuite/gna/issue2116/pkg15.vhdl new file mode 100644 index 000000000..c39b8f904 --- /dev/null +++ b/testsuite/gna/issue2116/pkg15.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return+0;end get;end gen0;package gen0 is +generic(package p is new k'g generic map(<>));function t return l;end gen0;package n is use p;end;package g is new k;package p is new n generic map(0);entity b is +end;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg2.vhdl b/testsuite/gna/issue2116/pkg2.vhdl new file mode 100644 index 000000000..c6041bdf0 --- /dev/null +++ b/testsuite/gna/issue2116/pkg2.vhdl @@ -0,0 +1,10 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end get;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new work.gen0;package g is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg3.vhdl b/testsuite/gna/issue2116/pkg3.vhdl new file mode 100644 index 000000000..3fe1114b8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg3.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin return 0;end get;end gen0;package n is generic(package p is new k'g generic map(<>));function g return n;end;package body gen0 is +use k;end gen0;package p is new w;package g is new k generic map(0);entity b is +end;architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg4.vhdl b/testsuite/gna/issue2116/pkg4.vhdl new file mode 100644 index 000000000..4a7ceef97 --- /dev/null +++ b/testsuite/gna/issue2116/pkg4.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package g is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg5.vhdl b/testsuite/gna/issue2116/pkg5.vhdl new file mode 100644 index 000000000..f3da2ed26 --- /dev/null +++ b/testsuite/gna/issue2116/pkg5.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new work.gen0;package g is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg6.vhdl b/testsuite/gna/issue2116/pkg6.vhdl new file mode 100644 index 000000000..68470c634 --- /dev/null +++ b/testsuite/gna/issue2116/pkg6.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen0 is +generic(package g is new k'g generic map(0));function g return n;end gen0;package body n is +use g;function g return n is +begin +end;end;package p is new w;package g is new o generic map(0);entity tb is +end tb;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg7.vhdl b/testsuite/gna/issue2116/pkg7.vhdl new file mode 100644 index 000000000..7e3c32180 --- /dev/null +++ b/testsuite/gna/issue2116/pkg7.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package g is new work.gen0;package p is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg8.vhdl b/testsuite/gna/issue2116/pkg8.vhdl new file mode 100644 index 000000000..ed1c3c49a --- /dev/null +++ b/testsuite/gna/issue2116/pkg8.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package g is new k'd;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg9.vhdl b/testsuite/gna/issue2116/pkg9.vhdl new file mode 100644 index 000000000..31b4273c8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg9.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new k'n;package g is new n generic map(0);architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl01.vhdl b/testsuite/gna/issue2116/psl01.vhdl new file mode 100644 index 000000000..ba00c112d --- /dev/null +++ b/testsuite/gna/issue2116/psl01.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!->0;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl02.vhdl b/testsuite/gna/issue2116/psl02.vhdl new file mode 100644 index 000000000..1f45c1b87 --- /dev/null +++ b/testsuite/gna/issue2116/psl02.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl03.vhdl b/testsuite/gna/issue2116/psl03.vhdl new file mode 100644 index 000000000..ea4c82c92 --- /dev/null +++ b/testsuite/gna/issue2116/psl03.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl04.vhdl b/testsuite/gna/issue2116/psl04.vhdl new file mode 100644 index 000000000..8e5835cef --- /dev/null +++ b/testsuite/gna/issue2116/psl04.vhdl @@ -0,0 +1,7 @@ +entity tb is +end; + +architecture behav of tb is +begin + assert 0!; +end behav; diff --git a/testsuite/gna/issue2116/sign01.vhdl b/testsuite/gna/issue2116/sign01.vhdl new file mode 100644 index 000000000..a0f46cfb0 --- /dev/null +++ b/testsuite/gna/issue2116/sign01.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(cl0:out signed(0 to 0));end hello;architecture behav of hello is +signal v:unsigned(0 to 0);begin +process(cl0)begin +if g[](0)then if 0='0'then +v;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/sign02.vhdl b/testsuite/gna/issue2116/sign02.vhdl new file mode 100644 index 000000000..1567be6f6 --- /dev/null +++ b/testsuite/gna/issue2116/sign02.vhdl @@ -0,0 +1,7 @@ +entity e is +end; + +architecture behav of e is +begin + assert g[](0); +end; diff --git a/testsuite/gna/issue2116/testsuite.sh b/testsuite/gna/issue2116/testsuite.sh new file mode 100755 index 000000000..3f79c4b5d --- /dev/null +++ b/testsuite/gna/issue2116/testsuite.sh @@ -0,0 +1,82 @@ +#! /bin/sh + +. ../../testenv.sh + +files=" +aspect01.vhdl +aspect02.vhdl +aspect03.vhdl +attr1.vhdl +attr10.vhdl +attr11.vhdl +attr12.vhdl +attr13.vhdl +attr14.vhdl +attr15.vhdl +attr16.vhdl +attr17.vhdl +attr18.vhdl +attr19.vhdl +attr2.vhdl +attr20.vhdl +attr21.vhdl +attr22.vhdl +attr23.vhdl +attr24.vhdl +attr25.vhdl +attr26.vhdl +attr3.vhdl +attr4.vhdl +attr5.vhdl +attr6.vhdl +attr7.vhdl +attr8.vhdl +attr9.vhdl +cons01.vhdl +cons02.vhdl +cons03.vhdl +err01.vhdl +eval1.vhdl +eval2.vhdl +func1.vhdl +func2.vhdl +func3.vhdl +func4.vhdl +func5.vhdl +func6.vhdl +func7.vhdl +name01.vhdl +name02.vhdl +pkg1.vhdl +pkg10.vhdl +pkg11.vhdl +pkg12.vhdl +pkg13.vhdl +pkg14.vhdl +pkg15.vhdl +pkg2.vhdl +pkg3.vhdl +pkg4.vhdl +pkg5.vhdl +pkg6.vhdl +pkg7.vhdl +pkg8.vhdl +pkg9.vhdl +psl01.vhdl +psl02.vhdl +psl03.vhdl +psl04.vhdl +sign01.vhdl +unit01.vhdl +unit02.vhdl +unit03.vhdl +" + +export GHDL_STD_FLAGS=--std=08 +for f in $files; do + analyze_failure $f +done + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2116/unit01.vhdl b/testsuite/gna/issue2116/unit01.vhdl new file mode 100644 index 000000000..37c3c92a2 --- /dev/null +++ b/testsuite/gna/issue2116/unit01.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);e0:std_logic;l:std_logic;r:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 downto 0);y:integer range 0 to 0;end record;signal i0:mystream_t;signal i:mystream_t;begin dataout<=min.x((0))(((0)));o generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/unit02.vhdl b/testsuite/gna/issue2116/unit02.vhdl new file mode 100644 index 000000000..e7b51518a --- /dev/null +++ b/testsuite/gna/issue2116/unit02.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);e0:std_logic;l:std_logic;r:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 downto 0);y:integer range 0 to 0;end record;signal m:mystream_t;signal i:mystream_t;begin dataout<=min.x((0));r(((0)));o generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/unit03.vhdl b/testsuite/gna/issue2116/unit03.vhdl new file mode 100644 index 000000000..4b846f0a6 --- /dev/null +++ b/testsuite/gna/issue2116/unit03.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);l:std_logic;r:std_logic;d:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +d:std_logic_vector(0 to 0);end record;signal m:mystream_t;signal i:mystream_t;begin dataout<=min.t((0))(((0)));o generic map(0);end architecture;
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