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-rw-r--r--testsuite/synth/issue1961/bug.vhdl34
-rw-r--r--testsuite/synth/issue1961/repro.vhdl30
-rwxr-xr-xtestsuite/synth/issue1961/testsuite.sh9
-rw-r--r--testsuite/synth/issue1968/dummy.vhdl23
-rw-r--r--testsuite/synth/issue1968/dummy_pkg.vhdl110
-rwxr-xr-xtestsuite/synth/issue1968/testsuite.sh8
-rw-r--r--testsuite/synth/issue1971/repro_bit_oper.vhdl8
-rwxr-xr-xtestsuite/synth/issue1971/testsuite.sh8
-rw-r--r--testsuite/synth/issue1972/ent.vhdl12
-rwxr-xr-xtestsuite/synth/issue1972/testsuite.sh7
-rwxr-xr-xtestsuite/synth/issue1977/testsuite.sh8
-rw-r--r--testsuite/synth/issue1977/triangularcounter.vhdl48
-rw-r--r--testsuite/synth/issue1978/reproducer.vhdl45
-rwxr-xr-xtestsuite/synth/issue1978/testsuite.sh8
14 files changed, 358 insertions, 0 deletions
diff --git a/testsuite/synth/issue1961/bug.vhdl b/testsuite/synth/issue1961/bug.vhdl
new file mode 100644
index 000000000..61a3593ed
--- /dev/null
+++ b/testsuite/synth/issue1961/bug.vhdl
@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+ port (
+ clk : in std_ulogic
+ );
+end bug;
+
+architecture struct of bug is
+
+ type a_t is record
+ value : unsigned;
+ end record;
+
+ type a_array_t is array(natural range<>) of a_t;
+
+ type b_t is record
+ a : a_array_t;
+ end record;
+
+ type b_array_t is array(natural range<>) of b_t;
+
+ function fun return natural is
+ variable b : b_array_t(0 to 1)(a(0 to 31)(value(31 downto 0)));
+ begin
+ return 0;
+ end function;
+
+ constant dummy : natural := fun;
+begin
+
+end architecture;
diff --git a/testsuite/synth/issue1961/repro.vhdl b/testsuite/synth/issue1961/repro.vhdl
new file mode 100644
index 000000000..4c2f7c290
--- /dev/null
+++ b/testsuite/synth/issue1961/repro.vhdl
@@ -0,0 +1,30 @@
+entity repro is
+ port (
+ clk : in bit
+ );
+end;
+
+architecture struct of repro is
+
+ type a_t is record
+ value : bit_vector;
+ end record;
+
+ type a_array_t is array(natural range<>) of a_t;
+
+ type b_t is record
+ a : a_array_t;
+ end record;
+
+ type b_array_t is array(natural range<>) of b_t;
+
+ function fun return natural is
+ variable b : b_array_t(0 to 1)(a(0 to 31)(value(31 downto 0)));
+ begin
+ return 0;
+ end function;
+
+ constant dummy : natural := fun;
+begin
+
+end architecture;
diff --git a/testsuite/synth/issue1961/testsuite.sh b/testsuite/synth/issue1961/testsuite.sh
new file mode 100755
index 000000000..0fee34170
--- /dev/null
+++ b/testsuite/synth/issue1961/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+exit 0
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only bug
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1968/dummy.vhdl b/testsuite/synth/issue1968/dummy.vhdl
new file mode 100644
index 000000000..2aa42e172
--- /dev/null
+++ b/testsuite/synth/issue1968/dummy.vhdl
@@ -0,0 +1,23 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.NUMERIC_STD.all;
+use work.dummy_pkg.all;
+
+entity dummy is
+ port (
+ signal A_i : in std_logic_vector(31 downto 0);
+ signal B_i : in std_logic_vector(31 downto 0);
+ signal C_i : in std_logic_vector(31 downto 0);
+ signal o : out std_logic_vector(31 downto 0)
+ );
+end dummy;
+
+architecture rtl of dummy is
+begin
+
+-- this_works(A_i, B_i, C_i, o);
+
+ this_doesnt_work(A_i, B_i, C_i, o);
+
+end rtl;
diff --git a/testsuite/synth/issue1968/dummy_pkg.vhdl b/testsuite/synth/issue1968/dummy_pkg.vhdl
new file mode 100644
index 000000000..bc9c3244f
--- /dev/null
+++ b/testsuite/synth/issue1968/dummy_pkg.vhdl
@@ -0,0 +1,110 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.NUMERIC_STD.all;
+
+package dummy_pkg is
+ type wordarray is array (natural range<>) of std_logic_vector(31 downto 0);
+
+ procedure p_csa (
+ variable A: in std_logic_vector(31 downto 0);
+ variable B: in std_logic_vector(31 downto 0);
+ variable Ci: in std_logic_vector(31 downto 0);
+ variable S: out std_logic_vector(31 downto 0);
+ variable Co: out std_logic_vector(31 downto 0)
+ );
+
+ function f_csa (
+ A : std_logic_vector(31 downto 0);
+ B: std_logic_vector(31 downto 0);
+ Ci: std_logic_vector(31 downto 0)
+ ) return wordarray;
+
+ procedure this_works (
+ signal A_i : in std_logic_vector(31 downto 0);
+ signal B_i : in std_logic_vector(31 downto 0);
+ signal C_i : in std_logic_vector(31 downto 0);
+ signal o : out std_logic_vector(31 downto 0)
+ );
+
+ procedure this_doesnt_work (
+ signal A_i : in std_logic_vector(31 downto 0);
+ signal B_i : in std_logic_vector(31 downto 0);
+ signal C_i : in std_logic_vector(31 downto 0);
+ signal o : out std_logic_vector(31 downto 0)
+ );
+
+end dummy_pkg;
+
+package body dummy_pkg is
+
+ procedure p_csa (
+ variable A: in std_logic_vector(31 downto 0);
+ variable B: in std_logic_vector(31 downto 0);
+ variable Ci: in std_logic_vector(31 downto 0);
+ variable S: out std_logic_vector(31 downto 0);
+ variable Co: out std_logic_vector(31 downto 0)
+ ) is
+ variable Co_tmp : std_logic_vector(32 downto 0);
+ begin
+ S := A xor B xor Ci;
+ Co_tmp := ((A and B) or (B and Ci) or (A and Ci)) & '0';
+ Co := Co_tmp(31 downto 0);
+ end procedure p_csa;
+
+ function f_csa (
+ A : std_logic_vector(31 downto 0);
+ B: std_logic_vector(31 downto 0);
+ Ci: std_logic_vector(31 downto 0)
+ ) return wordarray is
+ variable r : wordarray(1 downto 0);
+ variable Co_tmp : std_logic_vector(32 downto 0);
+ begin
+ r(0) := A xor B xor Ci;
+ Co_tmp := ((A and B) or (B and Ci) or (A and Ci)) & '0';
+ r(1) := Co_tmp(31 downto 0);
+ return r;
+ end function;
+
+ procedure this_works (
+ signal A_i : in std_logic_vector(31 downto 0);
+ signal B_i : in std_logic_vector(31 downto 0);
+ signal C_i : in std_logic_vector(31 downto 0);
+ signal o : out std_logic_vector(31 downto 0)
+ ) is
+ variable a : std_logic_vector(31 downto 0);
+ variable b : std_logic_vector(31 downto 0);
+ variable c : std_logic_vector(31 downto 0);
+ variable r0 : wordarray(1 downto 0);
+ variable s0 : std_logic_vector(31 downto 0);
+ variable c0 : std_logic_vector(31 downto 0);
+ begin
+ a := A_i;
+ b := B_i;
+ c := C_i;
+ r0 := f_csa(a, b, c);
+ s0 := r0(0);
+ c0 := r0(1);
+ o <= s0 + c0;
+ end procedure this_works;
+
+ procedure this_doesnt_work (
+ signal A_i : in std_logic_vector(31 downto 0);
+ signal B_i : in std_logic_vector(31 downto 0);
+ signal C_i : in std_logic_vector(31 downto 0);
+ signal o : out std_logic_vector(31 downto 0)
+ ) is
+ variable a : std_logic_vector(31 downto 0);
+ variable b : std_logic_vector(31 downto 0);
+ variable c : std_logic_vector(31 downto 0);
+ variable s0 : std_logic_vector(31 downto 0);
+ variable c0 : std_logic_vector(31 downto 0);
+ begin
+ a := A_i;
+ b := B_i;
+ c := C_i;
+ p_csa(a, b, c, s0, c0);
+ o <= s0 + c0;
+ end procedure this_doesnt_work;
+
+end dummy_pkg;
diff --git a/testsuite/synth/issue1968/testsuite.sh b/testsuite/synth/issue1968/testsuite.sh
new file mode 100755
index 000000000..9b5b1ea72
--- /dev/null
+++ b/testsuite/synth/issue1968/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth -fsynopsys dummy_pkg.vhdl dummy.vhdl -e > syn_dummy.vhdl
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1971/repro_bit_oper.vhdl b/testsuite/synth/issue1971/repro_bit_oper.vhdl
new file mode 100644
index 000000000..d5daa14cc
--- /dev/null
+++ b/testsuite/synth/issue1971/repro_bit_oper.vhdl
@@ -0,0 +1,8 @@
+entity repro_bit_oper is
+ port (x : in bit; y : out boolean);
+end;
+
+architecture a of repro_bit_oper is
+begin
+ y <= true when x else false;
+end;
diff --git a/testsuite/synth/issue1971/testsuite.sh b/testsuite/synth/issue1971/testsuite.sh
new file mode 100755
index 000000000..61a429361
--- /dev/null
+++ b/testsuite/synth/issue1971/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only repro_bit_oper
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1972/ent.vhdl b/testsuite/synth/issue1972/ent.vhdl
new file mode 100644
index 000000000..502f47785
--- /dev/null
+++ b/testsuite/synth/issue1972/ent.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+ port (output : out std_ulogic);
+end entity;
+
+architecture rtl of ent is
+ signal sr : std_ulogic_vector(0 downto 1);
+begin
+ output <= sr(1);
+end architecture;
diff --git a/testsuite/synth/issue1972/testsuite.sh b/testsuite/synth/issue1972/testsuite.sh
new file mode 100755
index 000000000..f6f8ea08f
--- /dev/null
+++ b/testsuite/synth/issue1972/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_failure ent.vhdl -e
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1977/testsuite.sh b/testsuite/synth/issue1977/testsuite.sh
new file mode 100755
index 000000000..665792ea1
--- /dev/null
+++ b/testsuite/synth/issue1977/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only triangularcounter
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1977/triangularcounter.vhdl b/testsuite/synth/issue1977/triangularcounter.vhdl
new file mode 100644
index 000000000..c1851de19
--- /dev/null
+++ b/testsuite/synth/issue1977/triangularcounter.vhdl
@@ -0,0 +1,48 @@
+library IEEE;
+context IEEE.IEEE_std_context;
+
+entity TriangularCounter is
+ generic (
+ g_Precision : natural := 11
+ );
+ port (
+ CLK : in std_logic;
+ RST : in std_logic;
+ EN : in std_logic;
+ REF : out unsigned(g_Precision-1 downto 0);
+ TRIGGER : out std_logic
+ );
+end entity;
+
+architecture arch of TriangularCounter is
+
+ signal dir : std_logic;
+ signal cnt : unsigned(REF'range);
+ signal tg_max : std_logic;
+ signal tg_min : std_logic;
+
+begin
+
+ process(RST, CLK)
+ begin
+ if RST then
+ cnt <= (others=>'0');
+ dir <= '0';
+ elsif rising_edge(CLK) then
+ if EN then
+ cnt <= cnt-1 when dir else cnt+1;
+ if tg_min or tg_max then
+ dir <= not dir;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ tg_max <= (not dir) and (cnt ?= to_unsigned(2**g_Precision-2, REF));
+ tg_min <= dir and (cnt ?= 1);
+
+ REF <= cnt;
+ TRIGGER <= tg_min;
+
+end architecture;
+
diff --git a/testsuite/synth/issue1978/reproducer.vhdl b/testsuite/synth/issue1978/reproducer.vhdl
new file mode 100644
index 000000000..38091541b
--- /dev/null
+++ b/testsuite/synth/issue1978/reproducer.vhdl
@@ -0,0 +1,45 @@
+--:file: Entity.vhd
+
+library IEEE;
+context IEEE.IEEE_std_context;
+
+entity Reproducer is
+ generic (
+ g_Precision : natural := 11;
+ g_PulsesPerRevolution : natural := 1000
+ );
+ port (
+ CLK : in std_logic;
+ RST : in std_logic;
+ EN : in std_logic;
+ Z : in std_logic;
+ POS : out unsigned(g_Precision-1 downto 0)
+ );
+end entity;
+
+architecture arch of Reproducer is
+
+ signal Position : unsigned(POS'range);
+
+ signal Direction : std_logic := '0';
+
+begin
+
+ PositionCounter: process(RST, Z, CLK)
+ constant CountLimit : unsigned(Position'range) := to_unsigned(4*g_PulsesPerRevolution-1, Position);
+ begin
+ if RST or Z then
+ Position <= (others => '0');
+ elsif rising_edge(CLK) and EN='1' then
+ Position <=
+ (others=>'0') when Position = CountLimit and Direction='1' else
+ CountLimit when Position = 0 and Direction='0' else
+ Position+1 when Direction else
+ Position-1;
+ end if;
+ end process;
+
+ pos <= position;
+ direction <= '0';
+
+end architecture;
diff --git a/testsuite/synth/issue1978/testsuite.sh b/testsuite/synth/issue1978/testsuite.sh
new file mode 100755
index 000000000..6755c8a4e
--- /dev/null
+++ b/testsuite/synth/issue1978/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_failure reproducer.vhdl -e
+
+echo "Test successful"
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-07 01:08:20 +0000