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-rw-r--r--testsuite/synth/slice01/tb_slice03.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/slice01/tb_slice03.vhdl b/testsuite/synth/slice01/tb_slice03.vhdl
new file mode 100644
index 000000000..a1e92cfe8
--- /dev/null
+++ b/testsuite/synth/slice01/tb_slice03.vhdl
@@ -0,0 +1,26 @@
+entity tb_slice03 is
+end tb_slice03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_slice03 is
+ signal di : std_logic_vector (7 downto 0);
+ signal do : std_logic_vector (3 downto 0);
+begin
+ dut: entity work.slice03
+ port map (di, do);
+
+ process
+ begin
+ di <= x"12";
+ wait for 1 ns;
+ assert do = x"1" severity error;
+
+ di <= x"e5";
+ wait for 1 ns;
+ assert do = x"e" severity error;
+
+ wait;
+ end process;
+end behav;