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Diffstat (limited to 'testsuite/synth/slice01/slice03.vhdl')
-rw-r--r-- | testsuite/synth/slice01/slice03.vhdl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/synth/slice01/slice03.vhdl b/testsuite/synth/slice01/slice03.vhdl new file mode 100644 index 000000000..0509efcbf --- /dev/null +++ b/testsuite/synth/slice01/slice03.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity slice03 is + port (di : std_logic_vector(7 downto 0); + do : out std_logic_vector (3 downto 0)); +end slice03; + +architecture behav of slice03 is +begin + do <= di (7 downto 4)(7 downto 4); +end behav; |