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-rw-r--r--testsuite/synth/ram01/sram01.vhdl29
1 files changed, 0 insertions, 29 deletions
diff --git a/testsuite/synth/ram01/sram01.vhdl b/testsuite/synth/ram01/sram01.vhdl
deleted file mode 100644
index b4bfd0d2e..000000000
--- a/testsuite/synth/ram01/sram01.vhdl
+++ /dev/null
@@ -1,29 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sram01 is
- port (
- clk_i : std_logic;
- addr_i : std_logic_vector(3 downto 0);
- data_i : std_logic_vector(7 downto 0);
- data_o : out std_logic_vector(7 downto 0);
- wen_i : std_logic);
-end sram01;
-
-architecture behav of sram01 is
-begin
- process (clk_i, addr_i)
- type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
- variable mem : mem_type;
- variable addr : natural range mem_type'range;
- begin
- if rising_edge(clk_i) then
- addr := to_integer (unsigned (addr_i));
- data_o <= mem (addr);
- if wen_i = '1' then
- mem (addr) := data_i;
- end if;
- end if;
- end process;
-end behav;