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-rw-r--r--testsuite/synth/psl02/verif4.vhdl10
1 files changed, 10 insertions, 0 deletions
diff --git a/testsuite/synth/psl02/verif4.vhdl b/testsuite/synth/psl02/verif4.vhdl
new file mode 100644
index 000000000..a8e4fff5a
--- /dev/null
+++ b/testsuite/synth/psl02/verif4.vhdl
@@ -0,0 +1,10 @@
+vunit verif4 (assert2(behav))
+{
+ default clock is rising_edge(clk);
+ function check_val (v : unsigned) return boolean is
+ begin
+ return v < 10;
+ end check_val;
+ assume always check_val (val);
+ assert always val /= 5 abort rst;
+}