1 files changed, 7 insertions, 1 deletions
diff --git a/testsuite/synth/issue662/psl_stable.vhdl b/testsuite/synth/issue662/psl_stable.vhdl
index 675cdbd56..36d0011f6 100644
--- a/testsuite/synth/issue662/psl_stable.vhdl
+++ b/testsuite/synth/issue662/psl_stable.vhdl
@@ -14,10 +14,16 @@ begin
   -- All is sensitive to rising edge of clk
   default clock is rising_edge(clk);
 
-  -- This assertion holds
+  -- This assertion should fail at cycle 13
   STABLE_0_a : assert always {not a; a} |=> (stable(c) until_ b);
 
   -- This assertion holds
   STABLE_1_a : assert always {not a; a} |=> (stable(d) until_ b);
 
+  -- This assertion should fail at cycle 13
+  STABLE_2_a : assert always {not a; a} |=> (c = prev(c) until_ b);
+
+  -- This assertion holds
+  STABLE_3_a : assert always {not a; a} |=> (d = prev(d) until_ b);
+
 end architecture psl;