1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/synth/issue662/psl_prev.vhdl b/testsuite/synth/issue662/psl_prev.vhdl
new file mode 100644
index 000000000..c9ddac35b
--- /dev/null
+++ b/testsuite/synth/issue662/psl_prev.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity psl_prev is
+  port (clk, a, b : std_logic);
+end entity psl_prev;
+
+
+architecture psl of psl_prev is
+begin
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion should fail
+  stable_1 : assert always (a -> prev(b) = b);
+end architecture psl;