1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/issue1271/issue2.vhdl b/testsuite/synth/issue1271/issue2.vhdl
new file mode 100644
index 000000000..1dd359c6c
--- /dev/null
+++ b/testsuite/synth/issue1271/issue2.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue is
+    port
+      (i_foo : in  std_logic;
+       o_foo : out std_logic;
+       clock : in  std_logic);
+end entity issue;
+
+architecture beh of issue is
+begin
+    process (clock)
+        variable v_foo : std_logic := i_foo;
+    begin
+        -- works without the if
+        if rising_edge (clock) then
+            v_foo := v_foo xor v_foo;
+            o_foo <= v_foo;
+        end if;
+    end process;
+end architecture;