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diff --git a/testsuite/synth/issue1168/bug.vhdl b/testsuite/synth/issue1168/bug.vhdl
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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+ generic(
+ LEN : positive := 32
+ );
+ port(
+ input_a : in unsigned(LEN-1 downto 0);
+ input_b : in unsigned(LEN-1 downto 0);
+ output : out unsigned(LEN-1 downto 0)
+ );
+end bug;
+
+architecture behav of bug is
+begin
+ output <= minimum(input_a, input_b);
+end architecture;