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-rw-r--r--testsuite/synth/dff01/dff12.vhdl25
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/dff01/dff12.vhdl b/testsuite/synth/dff01/dff12.vhdl
new file mode 100644
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--- /dev/null
+++ b/testsuite/synth/dff01/dff12.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff12 is
+ port (q : out std_logic;
+ d : std_logic;
+ clk : std_logic;
+ rstn : std_logic);
+end dff12;
+
+architecture behav of dff12 is
+ signal ff : std_logic := '1';
+begin
+ process (clk, rstn) is
+ begin
+ if rising_edge (clk) then
+ if rstn = '0' then
+ ff <= '0';
+ else
+ ff <= d;
+ end if;
+ end if;
+ end process;
+ q <= ff;
+end behav;