2 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/gna/issue874/crash.vhdl b/testsuite/gna/issue874/crash.vhdl
new file mode 100644
index 000000000..24ae9ee34
--- /dev/null
+++ b/testsuite/gna/issue874/crash.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.math_real.all;
+
+entity testbench is
+    generic(
+       c_clock_mhz :real    := 66.0
+    );
+end entity;
+
+architecture rtl of testbench is
+    constant c_ns_clock     :real    := (1.0/c_clock_mhz)*1000.0;
+    constant c_ns_write     :real    := 10.0;
+    constant c_ns_read      :real    := 25.0;
+
+begin
+
+-- synthesis translate_off
+process 
+begin
+    report "sram_ctrl2   c_ns_clock    :" & to_string(c_ns_clock, "%0.2f");
+    report "sram_ctrl2   c_ns_write    :" & to_string(c_ns_write, "%0.2f");
+    report "sram_ctrl2   c_ns_read     :" & to_string(c_ns_read, "%0.2f");
+	wait;
+end process;
+-- synthesis translate_on
+
+end architecture;  
diff --git a/testsuite/gna/issue874/testsuite.sh b/testsuite/gna/issue874/testsuite.sh
new file mode 100755
index 000000000..fca2b14d5
--- /dev/null
+++ b/testsuite/gna/issue874/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze crash.vhdl
+elab_simulate testbench
+
+clean
+
+echo "Test successful"