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diff --git a/testsuite/gna/issue50/idct.d/sync_ram.vhd b/testsuite/gna/issue50/idct.d/sync_ram.vhd
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+-- Simple generic RAM Model
+--
+-- +-----------------------------+
+-- |    Copyright 2008 DOULOS    |
+-- |   designer :  JK            |
+-- +-----------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sync_ram is
+  port (
+    clock   : in  std_logic;
+    we      : in  std_logic;
+    address : in  std_logic_vector;
+    datain  : in  std_logic_vector;
+    dataout : out std_logic_vector
+  );
+end entity sync_ram;
+
+architecture rtl of sync_ram is
+
+   type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
+   signal ram : ram_type;
+   signal read_address : std_logic_vector(address'range);
+
+begin
+
+  ramproc: process(clock) is
+  begin
+    if rising_edge(clock) then
+      if we = '1' then
+        ram(to_integer(unsigned(address))) <= datain;
+      end if;
+      read_address <= address;
+    end if;
+  end process ramproc;
+
+  dataout <= ram(to_integer(unsigned(read_address)));
+
+end architecture rtl;