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-rw-r--r--testsuite/gna/issue1131/repro.vhdl18
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/gna/issue1131/repro.vhdl b/testsuite/gna/issue1131/repro.vhdl
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+++ b/testsuite/gna/issue1131/repro.vhdl
@@ -0,0 +1,18 @@
+entity repro is
+ generic (
+ BUS_WIDTH : integer := 8);
+end entity;
+
+architecture Behav of repro is
+ type BusT is record
+ A : bit_vector;
+ F : bit_vector;
+ end record;
+
+ signal BusInst : BusT(
+ A(BUS_WIDTH-1 downto 0),
+ F(3 downto 0)
+ );
+begin
+
+end architecture;