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-rw-r--r--src/ghdldrv/ghdlsimul.adb6
-rw-r--r--src/simul/simul-main.adb132
-rw-r--r--src/simul/simul-main.ads39
-rw-r--r--src/simul/simul-vhdl_debug.adb5
-rw-r--r--src/simul/simul-vhdl_simul.adb102
-rw-r--r--src/simul/simul-vhdl_simul.ads12
6 files changed, 186 insertions, 110 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index a1f315678..475b19204 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -53,8 +53,10 @@ with Elab.Debugger;
with Synth.Flags;
with Synth.Errors;
with Synth.Vhdl_Foreign;
+
with Simul.Vhdl_Elab;
with Simul.Vhdl_Simul;
+with Simul.Main;
package body Ghdlsimul is
procedure Compile_Init (Analyze_Only : Boolean) is
@@ -234,9 +236,9 @@ package body Ghdlsimul is
elsif Option = "-t" then
Synth.Flags.Flag_Trace_Statements := True;
elsif Option = "-i" then
- Simul.Vhdl_Simul.Flag_Interractive := True;
+ Simul.Main.Flag_Interractive := True;
elsif Option = "-ge" then
- Simul.Vhdl_Simul.Flag_Debug_Elab := True;
+ Simul.Main.Flag_Debug_Elab := True;
elsif Option'Last > 3
and then Option (Option'First + 1) = 'g'
and then Is_Generic_Override_Option (Option)
diff --git a/src/simul/simul-main.adb b/src/simul/simul-main.adb
new file mode 100644
index 000000000..7ed10b001
--- /dev/null
+++ b/src/simul/simul-main.adb
@@ -0,0 +1,132 @@
+-- Simulation of VHDL
+-- Copyright (C) 2023 Tristan Gingold
+--
+-- This file is part of GHDL.
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <gnu.org/licenses>.
+
+with Areapools;
+
+with Synth.Flags;
+
+with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
+with Elab.Debugger;
+
+with Simul.Vhdl_Debug;
+with Simul.Vhdl_Elab;
+
+with Grt.Types; use Grt.Types;
+with Grt.Vhdl_Types; use Grt.Vhdl_Types;
+with Grt.Stdio;
+with Grt.Options;
+with Grt.Processes;
+with Grt.Errors;
+with Grt.Analog_Solver;
+with Grt.Main;
+
+package body Simul.Main is
+ Ghdl_Progname : constant String := "ghdl" & ASCII.Nul;
+
+ procedure Ghdl_Elaborate;
+ pragma Export (C, Ghdl_Elaborate, "__ghdl_ELABORATE");
+
+ procedure Ghdl_Elaborate is
+ begin
+ Elaborate_Proc.all;
+ end Ghdl_Elaborate;
+
+ procedure Simulation
+ is
+ Ok : C_Boolean;
+ Status : Integer;
+ begin
+ Break_Time := Std_Time'Last;
+ Break_Step := False;
+
+ Grt.Options.Progname := To_Ghdl_C_String (Ghdl_Progname'Address);
+ Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout);
+
+ Elab.Debugger.Error_Hook := Grt.Errors.Fatal_Error'Access;
+ Simul.Vhdl_Debug.Init;
+
+ pragma Assert (Areapools.Is_Empty (Expr_Pool));
+
+ if Flag_Debug_Elab then
+ Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
+ end if;
+
+ Ok := Grt.Main.Run_Elab;
+ if not Ok then
+ return;
+ end if;
+
+ pragma Assert (Areapools.Is_Empty (Expr_Pool));
+ pragma Assert (Areapools.Is_Empty (Process_Pool));
+
+ -- Copy flag.
+ Synth.Flags.Severity_Level := Grt.Options.Severity_Level;
+
+ -- Not supported.
+ Grt.Options.Trace_Signals := False;
+
+ if Flag_Interractive then
+ Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
+ end if;
+
+ Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout);
+
+ Status := Grt.Main.Run_Through_Longjump
+ (Grt.Processes.Simulation_Init'Access);
+
+ if Status = 0 then
+ if Grt.Processes.Flag_AMS then
+ Grt.Analog_Solver.Start;
+ end if;
+
+ pragma Assert (Areapools.Is_Empty (Expr_Pool));
+ pragma Assert (Areapools.Is_Empty (Process_Pool));
+
+ loop
+ if Break_Time < Grt.Processes.Next_Time then
+ Grt.Processes.Next_Time := Break_Time;
+ end if;
+
+ Status := Grt.Main.Run_Through_Longjump
+ (Grt.Processes.Simulation_Cycle'Access);
+ exit when Status < 0
+ or Status = Grt.Errors.Run_Stop
+ or Status = Grt.Errors.Run_Finished;
+
+ if Break_Step
+ or else (Current_Time >= Break_Time
+ and then Break_Time /= Std_Time'Last)
+ then
+ -- No not break anymore on time,
+ Break_Time := Std_Time'Last;
+ Break_Step := False;
+ Elab.Debugger.Debug_Time;
+ end if;
+
+ exit when Grt.Processes.Has_Simulation_Timeout;
+ end loop;
+ end if;
+
+ Grt.Main.Run_Finish (Status);
+ exception
+-- when Debugger_Quit =>
+-- null;
+ when Simulation_Finished =>
+ null;
+ end Simulation;
+end Simul.Main;
diff --git a/src/simul/simul-main.ads b/src/simul/simul-main.ads
new file mode 100644
index 000000000..74e624288
--- /dev/null
+++ b/src/simul/simul-main.ads
@@ -0,0 +1,39 @@
+-- Simulation of VHDL
+-- Copyright (C) 2023 Tristan Gingold
+--
+-- This file is part of GHDL.
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <gnu.org/licenses>.
+
+with Grt.Vhdl_Types;
+
+package Simul.Main is
+ Break_Time : Grt.Vhdl_Types.Std_Time;
+ Break_Step : Boolean;
+
+ Trace_Simulation : Boolean := False;
+
+ Flag_Interractive : Boolean := False;
+ Flag_Debug_Elab : Boolean := False;
+
+ type Elaborate_Acc is access procedure;
+
+ -- Procedure called for elaboration.
+ Elaborate_Proc : Elaborate_Acc;
+
+ -- Start and run simulation.
+ procedure Simulation;
+
+ Simulation_Finished : exception;
+end Simul.Main;
diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb
index 6ae5976ff..0d94be076 100644
--- a/src/simul/simul-vhdl_debug.adb
+++ b/src/simul/simul-vhdl_debug.adb
@@ -38,6 +38,7 @@ with Elab.Vhdl_Values; use Elab.Vhdl_Values;
with Elab.Vhdl_Values.Debug; use Elab.Vhdl_Values.Debug;
with Simul.Vhdl_Elab; use Simul.Vhdl_Elab;
with Simul.Vhdl_Simul;
+with Simul.Main;
with Grt.Types; use Grt.Types;
with Grt.Vhdl_Types; use Grt.Vhdl_Types;
@@ -788,14 +789,14 @@ package body Simul.Vhdl_Debug is
if P <= Line'Last then
L := Get_Word (Line, P);
if Line (P .. L) = "-s" then
- Simul.Vhdl_Simul.Break_Step := True;
+ Simul.Main.Break_Step := True;
else
Delta_Time := Grt.Options.Parse_Time (Line (P .. L));
if Delta_Time = -1 then
-- Error, ignore command.
return;
end if;
- Simul.Vhdl_Simul.Break_Time := Current_Time + Delta_Time;
+ Simul.Main.Break_Time := Current_Time + Delta_Time;
Grt.Processes.Next_Time := Current_Time + Delta_Time;
end if;
end if;
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index bbc6ab764..2d4c71c62 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -53,14 +53,13 @@ with Synth.Vhdl_Static_Proc;
with Synth.Flags;
with Synth.Ieee.Std_Logic_1164; use Synth.Ieee.Std_Logic_1164;
-with Simul.Vhdl_Debug;
+with Simul.Main;
with Grt.Types; use Grt.Types;
+with Grt.Vhdl_Types; use Grt.Vhdl_Types;
with Grt.Signals; use Grt.Signals;
with Grt.Options;
-with Grt.Stdio;
with Grt.Processes;
-with Grt.Main;
with Grt.Errors;
with Grt.Severity;
with Grt.Lib;
@@ -4141,103 +4140,18 @@ package body Simul.Vhdl_Simul is
Synth.Vhdl_Stmts.Hook_Create_Value_For_Signal_Individual_Assocs :=
Hook_Create_Value_For_Signal_Individual_Assocs'Access;
+ Assertion_Report_Handler := Assertion_Report_Msg'Access;
+
-- if Flag_Interractive then
-- Debug (Reason_Elab);
-- end if;
end Runtime_Elaborate;
- procedure Ghdl_Elaborate;
- pragma Export (C, Ghdl_Elaborate, "__ghdl_ELABORATE");
-
- procedure Ghdl_Elaborate is
- begin
- Runtime_Elaborate;
- end Ghdl_Elaborate;
-
- Ghdl_Progname : constant String := "ghdl" & ASCII.Nul;
-
- procedure Simulation
- is
- Ok : C_Boolean;
- Status : Integer;
+ procedure Simulation is
begin
- Break_Time := Std_Time'Last;
- Break_Step := False;
-
- Grt.Options.Progname := To_Ghdl_C_String (Ghdl_Progname'Address);
- Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout);
-
- Elab.Debugger.Error_Hook := Grt.Errors.Fatal_Error'Access;
- Simul.Vhdl_Debug.Init;
-
- pragma Assert (Areapools.Is_Empty (Expr_Pool));
-
- if Flag_Debug_Elab then
- Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
- end if;
-
- Ok := Grt.Main.Run_Elab;
- if not Ok then
- return;
- end if;
-
- pragma Assert (Areapools.Is_Empty (Expr_Pool));
- pragma Assert (Areapools.Is_Empty (Process_Pool));
-
- -- Copy flag.
- Synth.Flags.Severity_Level := Grt.Options.Severity_Level;
-
- -- Not supported.
- Grt.Options.Trace_Signals := False;
-
- if Flag_Interractive then
- Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
- end if;
-
- Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout);
- Assertion_Report_Handler := Assertion_Report_Msg'Access;
-
- Status := Grt.Main.Run_Through_Longjump
- (Grt.Processes.Simulation_Init'Access);
-
- if Status = 0 then
- if Grt.Processes.Flag_AMS then
- Grt.Analog_Solver.Start;
- end if;
-
- pragma Assert (Areapools.Is_Empty (Expr_Pool));
- pragma Assert (Areapools.Is_Empty (Process_Pool));
+ Simul.Main.Elaborate_Proc := Runtime_Elaborate'Access;
- loop
- if Break_Time < Grt.Processes.Next_Time then
- Grt.Processes.Next_Time := Break_Time;
- end if;
-
- Status := Grt.Main.Run_Through_Longjump
- (Grt.Processes.Simulation_Cycle'Access);
- exit when Status < 0
- or Status = Grt.Errors.Run_Stop
- or Status = Grt.Errors.Run_Finished;
-
- if Break_Step
- or else (Current_Time >= Break_Time
- and then Break_Time /= Std_Time'Last)
- then
- -- No not break anymore on time,
- Break_Time := Std_Time'Last;
- Break_Step := False;
- Elab.Debugger.Debug_Time;
- end if;
-
- exit when Grt.Processes.Has_Simulation_Timeout;
- end loop;
- end if;
-
- Grt.Main.Run_Finish (Status);
- exception
--- when Debugger_Quit =>
--- null;
- when Simulation_Finished =>
- null;
+ Simul.Main.Simulation;
end Simulation;
+
end Simul.Vhdl_Simul;
diff --git a/src/simul/simul-vhdl_simul.ads b/src/simul/simul-vhdl_simul.ads
index 47c1273be..713875b0c 100644
--- a/src/simul/simul-vhdl_simul.ads
+++ b/src/simul/simul-vhdl_simul.ads
@@ -22,8 +22,6 @@ with Areapools;
with Vhdl.Nodes; use Vhdl.Nodes;
-with Grt.Vhdl_Types; use Grt.Vhdl_Types;
-
with Elab.Memtype; use Elab.Memtype;
with Elab.Vhdl_Context; use Elab.Vhdl_Context;
@@ -32,14 +30,6 @@ with Simul.Vhdl_Elab; use Simul.Vhdl_Elab;
with Grt.Signals;
package Simul.Vhdl_Simul is
- Break_Time : Std_Time;
- Break_Step : Boolean;
-
- Trace_Simulation : Boolean := False;
-
- Flag_Interractive : Boolean := False;
- Flag_Debug_Elab : Boolean := False;
-
Trace_Residues : Boolean := False;
type Process_Kind is (Kind_Process, Kind_PSL);
@@ -85,8 +75,6 @@ package Simul.Vhdl_Simul is
-- If true, disp current time in assert message.
Disp_Time_Before_Values: Boolean := False;
- Simulation_Finished : exception;
-
procedure Simulation;
-- Low level functions, for debugger.
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 09:13:36 +0000