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-rw-r--r--src/synth/elab-vhdl_expr.adb5
-rw-r--r--src/synth/synth-vhdl_aggr.adb8
-rw-r--r--src/synth/synth-vhdl_context.ads2
-rw-r--r--src/synth/synth-vhdl_decls.adb7
-rw-r--r--src/synth/synth-vhdl_expr.adb22
-rw-r--r--src/synth/synth-vhdl_expr.ads7
-rw-r--r--src/synth/synth-vhdl_insts.adb4
-rw-r--r--src/synth/synth-vhdl_oper.adb16
-rw-r--r--src/synth/synth-vhdl_stmts.adb17
9 files changed, 35 insertions, 53 deletions
diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb
index d1b44fe78..391a75c92 100644
--- a/src/synth/elab-vhdl_expr.adb
+++ b/src/synth/elab-vhdl_expr.adb
@@ -20,7 +20,7 @@ with Types; use Types;
with Name_Table;
with Str_Table;
-with Netlists.Builders;
+with Netlists;
with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Utils; use Vhdl.Utils;
@@ -101,8 +101,7 @@ package body Elab.Vhdl_Expr is
Bounds : Boolean;
Loc : Node) return Valtyp is
begin
- return Synth_Subtype_Conversion
- (Netlists.Builders.No_Context, Vt, Dtype, Bounds, Loc);
+ return Synth_Subtype_Conversion (null, Vt, Dtype, Bounds, Loc);
end Exec_Subtype_Conversion;
function Exec_Value_Attribute (Syn_Inst : Synth_Instance_Acc; Attr : Node)
diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb
index bb355726e..bd198e944 100644
--- a/src/synth/synth-vhdl_aggr.adb
+++ b/src/synth/synth-vhdl_aggr.adb
@@ -121,7 +121,6 @@ package body Synth.Vhdl_Aggr is
Const_P : out Boolean;
Err_P : out boolean)
is
- Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Bound : constant Bound_Type := Get_Array_Bound (Typ);
El_Typ : constant Type_Acc := Get_Array_Element (Typ);
Stride : constant Nat32 := Strides (Dim);
@@ -141,7 +140,8 @@ package body Synth.Vhdl_Aggr is
if Typ.Alast then
pragma Assert (Dim = Strides'Last);
Val := Synth_Expression_With_Type (Syn_Inst, Value, El_Typ);
- Val := Synth_Subtype_Conversion (Ctxt, Val, El_Typ, False, Value);
+ Val := Synth_Subtype_Conversion
+ (Syn_Inst, Val, El_Typ, False, Value);
pragma Assert (Res (Pos) = No_Valtyp);
Res (Pos) := Val;
if Val = No_Valtyp then
@@ -345,7 +345,6 @@ package body Synth.Vhdl_Aggr is
Err_P : out Boolean;
Const_P : out Boolean)
is
- Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Value : Node;
Assoc : Node;
Pos : Nat32;
@@ -361,7 +360,8 @@ package body Synth.Vhdl_Aggr is
if Const_P and not Is_Static (Val.Val) then
Const_P := False;
end if;
- Val := Synth_Subtype_Conversion (Ctxt, Val, El_Type, False, Value);
+ Val := Synth_Subtype_Conversion
+ (Syn_Inst, Val, El_Type, False, Value);
if Val = No_Valtyp then
Err_P := True;
return;
diff --git a/src/synth/synth-vhdl_context.ads b/src/synth/synth-vhdl_context.ads
index 59f18f960..2b4571c23 100644
--- a/src/synth/synth-vhdl_context.ads
+++ b/src/synth/synth-vhdl_context.ads
@@ -45,7 +45,7 @@ package Synth.Vhdl_Context is
Base : Base_Instance_Acc;
Name : Sname := No_Sname);
- procedure Set_Extra (Inst :Synth_Instance_Acc;
+ procedure Set_Extra (Inst : Synth_Instance_Acc;
Parent : Synth_Instance_Acc;
Name : Sname := No_Sname);
diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb
index dfbedff91..6bf730e35 100644
--- a/src/synth/synth-vhdl_decls.adb
+++ b/src/synth/synth-vhdl_decls.adb
@@ -128,7 +128,6 @@ package body Synth.Vhdl_Decls is
Is_Subprg : Boolean;
Last_Type : in out Node)
is
- Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Deferred_Decl : constant Node := Get_Deferred_Declaration (Decl);
First_Decl : Node;
Decl_Type : Node;
@@ -176,7 +175,7 @@ package body Synth.Vhdl_Decls is
Set_Error (Syn_Inst);
return;
end if;
- Val := Synth_Subtype_Conversion (Ctxt, Val, Obj_Type, True, Decl);
+ Val := Synth_Subtype_Conversion (Syn_Inst, Val, Obj_Type, True, Decl);
-- For constant functions, the value must be constant.
pragma Assert (not Get_Instance_Const (Syn_Inst)
or else Is_Static (Val.Val));
@@ -399,7 +398,7 @@ package body Synth.Vhdl_Decls is
if Is_Valid (Def) then
Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Typ);
Init := Synth_Subtype_Conversion
- (Ctxt, Init, Obj_Typ, True, Decl);
+ (Syn_Inst, Init, Obj_Typ, True, Decl);
if not Is_Subprg
and then not Is_Static (Init.Val)
then
@@ -501,7 +500,7 @@ package body Synth.Vhdl_Decls is
Res := Create_Value_Alias (Base, Off, Typ);
end if;
if Obj_Typ /= null then
- Res := Synth_Subtype_Conversion (Ctxt, Res, Obj_Typ, True, Decl);
+ Res := Synth_Subtype_Conversion (Syn_Inst, Res, Obj_Typ, True, Decl);
end if;
Create_Object (Syn_Inst, Decl, Res);
end Synth_Object_Alias_Declaration;
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index 655269111..62f41d3b5 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -513,7 +513,7 @@ package body Synth.Vhdl_Expr is
end case;
end Reshape_Value;
- function Synth_Subtype_Conversion (Ctxt : Context_Acc;
+ function Synth_Subtype_Conversion (Syn_Inst : Synth_Instance_Acc;
Vt : Valtyp;
Dtype : Type_Acc;
Bounds : Boolean;
@@ -547,6 +547,7 @@ package body Synth.Vhdl_Expr is
-- Truncate.
-- TODO: check overflow.
declare
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
N : Net;
begin
if Is_Static_Val (Vt.Val) then
@@ -569,7 +570,7 @@ package body Synth.Vhdl_Expr is
end if;
when Value_Const =>
return Synth_Subtype_Conversion
- (Ctxt, (Vt.Typ, Vt.Val.C_Val), Dtype, Bounds, Loc);
+ (Syn_Inst, (Vt.Typ, Vt.Val.C_Val), Dtype, Bounds, Loc);
when Value_Memory =>
-- Check for overflow.
declare
@@ -577,6 +578,7 @@ package body Synth.Vhdl_Expr is
begin
if not In_Range (Dtype.Drange, Val) then
Error_Msg_Synth (+Loc, "value out of range");
+ Elab.Debugger.Debug_Error (Syn_Inst, Loc);
return No_Valtyp;
end if;
return Create_Value_Discrete (Val, Dtype);
@@ -655,18 +657,6 @@ package body Synth.Vhdl_Expr is
end case;
end Synth_Subtype_Conversion;
- function Synth_Subtype_Conversion (Syn_Inst : Synth_Instance_Acc;
- Vt : Valtyp;
- Dtype : Type_Acc;
- Bounds : Boolean;
- Loc : Source.Syn_Src)
- return Valtyp
- is
- Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
- begin
- return Synth_Subtype_Conversion (Ctxt, Vt, Dtype, Bounds, Loc);
- end Synth_Subtype_Conversion;
-
function Synth_Name (Syn_Inst : Synth_Instance_Acc; Name : Node)
return Valtyp is
begin
@@ -2155,7 +2145,6 @@ package body Synth.Vhdl_Expr is
when Iir_Kind_Pos_Attribute
| Iir_Kind_Val_Attribute =>
declare
- Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Param : constant Node := Get_Parameter (Expr);
V : Valtyp;
Dtype : Type_Acc;
@@ -2164,7 +2153,8 @@ package body Synth.Vhdl_Expr is
Dtype := Get_Subtype_Object (Syn_Inst, Get_Type (Expr));
-- FIXME: to be generalized. Not always as simple as a
-- subtype conversion.
- return Synth_Subtype_Conversion (Ctxt, V, Dtype, False, Expr);
+ return Synth_Subtype_Conversion
+ (Syn_Inst, V, Dtype, False, Expr);
end;
when Iir_Kind_Low_Type_Attribute =>
return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Dir_To);
diff --git a/src/synth/synth-vhdl_expr.ads b/src/synth/synth-vhdl_expr.ads
index f5d9fa7a0..846c8409c 100644
--- a/src/synth/synth-vhdl_expr.ads
+++ b/src/synth/synth-vhdl_expr.ads
@@ -34,13 +34,6 @@ with Synth.Source;
package Synth.Vhdl_Expr is
-- Perform a subtype conversion. Check constraints.
- function Synth_Subtype_Conversion (Ctxt : Context_Acc;
- Vt : Valtyp;
- Dtype : Type_Acc;
- Bounds : Boolean;
- Loc : Source.Syn_Src)
- return Valtyp;
-
function Synth_Subtype_Conversion (Syn_Inst : Synth_Instance_Acc;
Vt : Valtyp;
Dtype : Type_Acc;
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb
index 75fb5f00d..9c88861a2 100644
--- a/src/synth/synth-vhdl_insts.adb
+++ b/src/synth/synth-vhdl_insts.adb
@@ -674,7 +674,7 @@ package body Synth.Vhdl_Insts is
Act := Synth_Expression_With_Type (Act_Inst, Actual, Inter_Typ);
end if;
- Act := Synth_Subtype_Conversion (Ctxt, Act, Inter_Typ, False, Assoc);
+ Act := Synth_Subtype_Conversion (Act_Inst, Act, Inter_Typ, False, Assoc);
return Act;
end Synth_Single_Input_Assoc;
@@ -1475,7 +1475,7 @@ package body Synth.Vhdl_Insts is
Inter_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Inter));
Init := Synth_Expression_With_Type (Syn_Inst, Default, Inter_Typ);
Init := Synth_Subtype_Conversion
- (Ctxt, Init, Inter_Typ, False, Inter);
+ (Syn_Inst, Init, Inter_Typ, False, Inter);
Init_Net := Get_Net (Ctxt, Init);
else
Init_Net := No_Net;
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb
index 920729c44..78952cf5c 100644
--- a/src/synth/synth-vhdl_oper.adb
+++ b/src/synth/synth-vhdl_oper.adb
@@ -723,12 +723,13 @@ package body Synth.Vhdl_Oper is
if Left = No_Valtyp then
return No_Valtyp;
end if;
- Left := Synth_Subtype_Conversion (Ctxt, Left, Left_Typ, False, Expr);
+ Left := Synth_Subtype_Conversion (Syn_Inst, Left, Left_Typ, False, Expr);
Right := Synth_Expression_With_Type (Syn_Inst, Right_Expr, Right_Typ);
if Right = No_Valtyp then
return No_Valtyp;
end if;
- Right := Synth_Subtype_Conversion (Ctxt, Right, Right_Typ, False, Expr);
+ Right := Synth_Subtype_Conversion
+ (Syn_Inst, Right, Right_Typ, False, Expr);
if Is_Static_Val (Left.Val) and Is_Static_Val (Right.Val) then
Srec := Eval_Static_Dyadic_Predefined
@@ -1663,7 +1664,7 @@ package body Synth.Vhdl_Oper is
return No_Valtyp;
end if;
Operand := Synth_Subtype_Conversion
- (Ctxt, Operand, Oper_Typ, False, Loc);
+ (Syn_Inst, Operand, Oper_Typ, False, Loc);
Strip_Const (Operand);
if Is_Static_Val (Operand.Val) then
@@ -1766,12 +1767,13 @@ package body Synth.Vhdl_Oper is
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Shift_Rotate;
- function Synth_Find_Bit (Ctxt : Context_Acc;
+ function Synth_Find_Bit (Syn_Inst : Synth_Instance_Acc;
Left, Right : Valtyp;
Res_Typ : Type_Acc;
Leftmost : Boolean;
Expr : Node) return Valtyp
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
pragma Assert (Left.Typ.Kind = Type_Vector);
Len : constant Uns32 := Left.Typ.Abound.Len;
Max : Int32;
@@ -1831,7 +1833,7 @@ package body Synth.Vhdl_Oper is
end;
end loop;
- return Synth_Subtype_Conversion (Ctxt, Create_Value_Net (Res, Typ),
+ return Synth_Subtype_Conversion (Syn_Inst, Create_Value_Net (Res, Typ),
Res_Typ, False, Expr);
end Synth_Find_Bit;
@@ -2144,10 +2146,10 @@ package body Synth.Vhdl_Oper is
when Iir_Predefined_Ieee_Numeric_Std_Find_Leftmost_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Find_Leftmost_Uns =>
- return Synth_Find_Bit (Ctxt, L, R, Res_Typ, True, Expr);
+ return Synth_Find_Bit (Subprg_Inst, L, R, Res_Typ, True, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Find_Rightmost_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Find_Rightmost_Uns =>
- return Synth_Find_Bit (Ctxt, L, R, Res_Typ, False, Expr);
+ return Synth_Find_Bit (Subprg_Inst, L, R, Res_Typ, False, Expr);
when others =>
Error_Msg_Synth
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index eb6ddedaf..68acfc94d 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -93,7 +93,7 @@ package body Synth.Vhdl_Stmts is
Res := Synth_Expression_With_Type
(Syn_Inst, Get_We_Value (Wf), Targ_Type);
Res := Synth_Subtype_Conversion
- (Get_Build (Syn_Inst), Res, Targ_Type, False, Wf);
+ (Syn_Inst, Res, Targ_Type, False, Wf);
return Res;
end if;
end Synth_Waveform;
@@ -607,10 +607,10 @@ package body Synth.Vhdl_Stmts is
Val : Valtyp;
Loc : Node)
is
- Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
V : Valtyp;
begin
- V := Synth_Subtype_Conversion (Ctxt, Val, Target.Targ_Type, False, Loc);
+ V := Synth_Subtype_Conversion
+ (Syn_Inst, Val, Target.Targ_Type, False, Loc);
pragma Unreferenced (Val);
if V = No_Valtyp then
-- In case of error.
@@ -819,7 +819,7 @@ package body Synth.Vhdl_Stmts is
(Inst, Get_Expression (Ce), Targ_Type);
-- Convert to the target subtype so that all the conditional
-- expressions have the same width.
- Val := Synth_Subtype_Conversion (Ctxt, Val, Targ_Type, False, Ce);
+ Val := Synth_Subtype_Conversion (Inst, Val, Targ_Type, False, Ce);
if Cond_Tri = True and then First = No_Valtyp then
-- This is the first and only value.
@@ -1001,7 +1001,7 @@ package body Synth.Vhdl_Stmts is
V := Synth_Expression_With_Basetype
(Syn_Inst, Get_Choice_Expression (Choice));
V := Synth_Subtype_Conversion
- (Ctxt, V, Choice_Typ, False, Choice);
+ (Syn_Inst, V, Choice_Typ, False, Choice);
if Ignore_Choice_Expression (V, Choice) then
Cond := No_Net;
else
@@ -1845,7 +1845,6 @@ package body Synth.Vhdl_Stmts is
Caller_Inst : Synth_Instance_Acc;
Init : Association_Iterator_Init)
is
- Ctxt : constant Context_Acc := Get_Build (Caller_Inst);
Inter : Node;
Inter_Type : Type_Acc;
Assoc : Node;
@@ -1930,7 +1929,7 @@ package body Synth.Vhdl_Stmts is
if Get_Mode (Inter) /= Iir_Out_Mode then
-- Always passed by value
Val := Synth_Subtype_Conversion
- (Ctxt, Val, Inter_Type, True, Assoc);
+ (Subprg_Inst, Val, Inter_Type, True, Assoc);
else
-- Use default value ?
null;
@@ -1974,7 +1973,7 @@ package body Synth.Vhdl_Stmts is
-- This is equivalent to subtype conversion for non-scalar
-- types.
Val := Synth_Subtype_Conversion
- (Ctxt, Val, Inter_Type, True, Assoc);
+ (Subprg_Inst, Val, Inter_Type, True, Assoc);
end if;
when Iir_Kind_Interface_File_Declaration =>
null;
@@ -2987,7 +2986,7 @@ package body Synth.Vhdl_Stmts is
return;
end if;
- Val := Synth_Subtype_Conversion (Ctxt, Val, C.Ret_Typ, True, Stmt);
+ Val := Synth_Subtype_Conversion (C.Inst, Val, C.Ret_Typ, True, Stmt);
if C.Nbr_Ret = 0 then
C.Ret_Value := Val;
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 14:23:14 +0000