diff options
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/translate/trans-chap9.adb | 18 | ||||
| -rw-r--r-- | src/vhdl/translate/translation.adb | 14 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 31 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes_meta.adb | 170 | ||||
| -rw-r--r-- | src/vhdl/vhdl-prints.adb | 9 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 27 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_stmts.adb | 11 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_stmts.ads | 3 |
9 files changed, 154 insertions, 131 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index d6c6ba0ff..ae768b3d0 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -477,7 +477,7 @@ package body Simul.Simulation.Main is S_Num := Get_State_Label (S); pragma Assert (S_Num = Get_PSL_Nbr_States (E.Stmt) - 1); case Get_Kind (E.Stmt) is - when Iir_Kind_Psl_Assume_Directive => + when Iir_Kind_Psl_Assert_Directive => if Nvec (S_Num) then Execute_Failed_Assertion (E.Instance, "psl assertion", E.Stmt, diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb index 7a2033624..c3d3a1af0 100644 --- a/src/vhdl/translate/trans-chap9.adb +++ b/src/vhdl/translate/trans-chap9.adb @@ -507,6 +507,18 @@ package body Trans.Chap9 is Finish_Subprogram_Body; end Translate_Psl_Report; + procedure Call_Psl_Fail (Stmt : Iir; Subprg : O_Dnode) + is + Assocs : O_Assoc_List; + Loc : O_Dnode; + begin + Loc := Chap4.Get_Location (Stmt); + Start_Association (Assocs, Subprg); + New_Association (Assocs, New_Address (New_Obj (Loc), + Ghdl_Location_Ptr_Node)); + New_Procedure_Call (Assocs); + end Call_Psl_Fail; + procedure Translate_Psl_Directive_Statement (Stmt : Iir; Base : Block_Info_Acc) is @@ -648,8 +660,7 @@ package body Trans.Chap9 is Chap8.Translate_Report (Stmt, Ghdl_Psl_Assert_Failed, Severity_Level_Error); when Iir_Kind_Psl_Assume_Directive => - Chap8.Translate_Report - (Stmt, Ghdl_Psl_Assume_Failed, Severity_Level_Error); + Call_Psl_Fail (Stmt, Ghdl_Psl_Assume_Failed); when Iir_Kind_Psl_Cover_Directive => if Get_Report_Expression (Stmt) /= Null_Iir then Start_Association (Assocs, Report_Proc); @@ -732,8 +743,7 @@ package body Trans.Chap9 is Chap8.Translate_Report (Stmt, Ghdl_Psl_Assert_Failed, Severity_Level_Error); else - Chap8.Translate_Report - (Stmt, Ghdl_Psl_Assume_Failed, Severity_Level_Error); + Call_Psl_Fail (Stmt, Ghdl_Psl_Assume_Failed); end if; New_Return_Stmt; Finish_If_Stmt (E_Blk); diff --git a/src/vhdl/translate/translation.adb b/src/vhdl/translate/translation.adb index 863acd37d..7bb16a17b 100644 --- a/src/vhdl/translate/translation.adb +++ b/src/vhdl/translate/translation.adb @@ -1070,6 +1070,15 @@ package body Translation is Ghdl_Location_Ptr_Node); Finish_Subprogram_Decl (Interfaces, Subprg); end Create_Report_Subprg; + + procedure Create_Fail_Subprg (Name : String; Subprg : out O_Dnode) is + begin + Start_Procedure_Decl + (Interfaces, Get_Identifier (Name), O_Storage_External); + New_Interface_Decl (Interfaces, Param, Get_Identifier ("location"), + Ghdl_Location_Ptr_Node); + Finish_Subprogram_Decl (Interfaces, Subprg); + end Create_Fail_Subprg; begin Create_Report_Subprg ("__ghdl_assert_failed", Ghdl_Assert_Failed); @@ -1077,12 +1086,13 @@ package body Translation is ("__ghdl_ieee_assert_failed", Ghdl_Ieee_Assert_Failed); Create_Report_Subprg ("__ghdl_psl_assert_failed", Ghdl_Psl_Assert_Failed); - Create_Report_Subprg ("__ghdl_psl_assume_failed", - Ghdl_Psl_Assume_Failed); Create_Report_Subprg ("__ghdl_psl_cover", Ghdl_Psl_Cover); Create_Report_Subprg ("__ghdl_psl_cover_failed", Ghdl_Psl_Cover_Failed); Create_Report_Subprg ("__ghdl_report", Ghdl_Report); + + Create_Fail_Subprg ("__ghdl_psl_assume_failed", + Ghdl_Psl_Assume_Failed); end; -- procedure __ghdl_check_stack_allocation (size : __ghdl_index_type) diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index c905d94ae..73cc7d4aa 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -655,8 +655,8 @@ package Vhdl.Nodes is -- LRM08 7.3 Configuration specification -- -- configuration_specification ::= - -- simple_configuration_specification - -- | compound_configuration_specification + -- simple_configuration_specification + -- | compound_configuration_specification -- -- simple_configuration_specification ::= -- FOR component_specification binding_indication ; @@ -672,9 +672,9 @@ package Vhdl.Nodes is -- instantiation_list : component_name -- -- instantiation_list ::= - -- instantiation_label { , instantiation_label } - -- | OTHERS - -- | ALL + -- instantiation_label { , instantiation_label } + -- | OTHERS + -- | ALL -- -- The location points to 'for'. -- @@ -1407,7 +1407,7 @@ package Vhdl.Nodes is -- -- Get/Set_Chain (Field2) -- - -- For string, the identifier is the corresponding reserved word. + -- For string, the identifier is the corresponding reserved word. -- Get/Set_Identifier (Field3) -- -- Get/Set_Subprogram_Hash (Field4) @@ -1416,7 +1416,7 @@ package Vhdl.Nodes is -- -- Get/Set_Generic_Chain (Field6) -- - -- --Get/Set_Generic_Map_Aspect_Chain (Field8) + -- --Get/Set_Generic_Map_Aspect_Chain (Field8) -- -- Get/Set_Implicit_Definition (Field7) -- @@ -1458,8 +1458,8 @@ package Vhdl.Nodes is -- Only for Iir_Kind_Procedure_Declaration: -- Get/Set_Suspend_Flag (Flag11) -- - -- For an explicit subprogram: true if the declaration is an homograph of - -- an implicit operation of a type. + -- For an explicit subprogram: true if the declaration is an homograph of + -- an implicit operation of a type. -- Get/Set_Hide_Implicit_Flag (Flag12) -- -- Get/Set_Wait_State (State1) @@ -1539,7 +1539,7 @@ package Vhdl.Nodes is -- -- Get/Set_Chain (Field2) -- - -- For string, the identifier is the corresponding reserved word. + -- For string, the identifier is the corresponding reserved word. -- Get/Set_Identifier (Field3) -- -- Get/Set_Subprogram_Hash (Field4) @@ -1697,8 +1697,8 @@ package Vhdl.Nodes is -- declaration. -- Get/Set_Default_Value (Field4) -- - -- Note that the type may be extracted from the default_value if the subtype - -- indication is unconstrained. + -- Note that the type may be extracted from the default_value if the + -- subtype indication is unconstrained. -- Get/Set_Type (Field1) -- -- Only for Iir_Kind_Constant_Declaration: @@ -2926,6 +2926,7 @@ package Vhdl.Nodes is -- Get/Set_Severity_Expression (Field4) -- -- Only for Iir_Kind_Psl_Assert_Directive: + -- Only for Iir_Kind_Psl_Cover_Directive: -- Get/Set_Report_Expression (Field5) -- -- The following fields are set by canon. @@ -3664,8 +3665,8 @@ package Vhdl.Nodes is -- LRM08 9.3.7 Allocators -- -- allocator ::= - -- NEW subtype_indication - -- | NEW qualified_expression + -- NEW subtype_indication + -- | NEW qualified_expression -- -- Get/Set_Type (Field1) -- @@ -3871,7 +3872,7 @@ package Vhdl.Nodes is -- -- Get/Set_Identifier (Field3) -- - -- The selected element. + -- The selected element. -- Get/Set_Named_Entity (Field4) -- -- Get/Set_Base_Name (Field5) diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index d7e9e1433..4a933e382 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -3834,6 +3834,7 @@ package body Vhdl.Nodes_Meta is Field_Visible_Flag, Field_Parent, Field_Chain, + Field_Report_Expression, Field_PSL_Clock_Sensitivity, -- Iir_Kind_Psl_Restrict_Directive Field_Psl_Sequence, @@ -4654,90 +4655,90 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Concurrent_Procedure_Call_Statement => 1385, Iir_Kind_Psl_Assert_Directive => 1398, Iir_Kind_Psl_Assume_Directive => 1409, - Iir_Kind_Psl_Cover_Directive => 1420, - Iir_Kind_Psl_Restrict_Directive => 1431, - Iir_Kind_Block_Statement => 1445, - Iir_Kind_If_Generate_Statement => 1456, - Iir_Kind_Case_Generate_Statement => 1465, - Iir_Kind_For_Generate_Statement => 1474, - Iir_Kind_Component_Instantiation_Statement => 1485, - Iir_Kind_Psl_Default_Clock => 1489, - Iir_Kind_Simple_Simultaneous_Statement => 1496, - Iir_Kind_Generate_Statement_Body => 1507, - Iir_Kind_If_Generate_Else_Clause => 1513, - Iir_Kind_Simple_Signal_Assignment_Statement => 1523, - Iir_Kind_Conditional_Signal_Assignment_Statement => 1533, - Iir_Kind_Selected_Waveform_Assignment_Statement => 1544, - Iir_Kind_Null_Statement => 1548, - Iir_Kind_Assertion_Statement => 1555, - Iir_Kind_Report_Statement => 1561, - Iir_Kind_Wait_Statement => 1569, - Iir_Kind_Variable_Assignment_Statement => 1576, - Iir_Kind_Conditional_Variable_Assignment_Statement => 1583, - Iir_Kind_Return_Statement => 1589, - Iir_Kind_For_Loop_Statement => 1598, - Iir_Kind_While_Loop_Statement => 1607, - Iir_Kind_Next_Statement => 1614, - Iir_Kind_Exit_Statement => 1621, - Iir_Kind_Case_Statement => 1629, - Iir_Kind_Procedure_Call_Statement => 1635, - Iir_Kind_If_Statement => 1645, - Iir_Kind_Elsif => 1651, - Iir_Kind_Character_Literal => 1659, - Iir_Kind_Simple_Name => 1667, - Iir_Kind_Selected_Name => 1676, - Iir_Kind_Operator_Symbol => 1682, - Iir_Kind_Reference_Name => 1686, - Iir_Kind_External_Constant_Name => 1694, - Iir_Kind_External_Signal_Name => 1702, - Iir_Kind_External_Variable_Name => 1711, - Iir_Kind_Selected_By_All_Name => 1717, - Iir_Kind_Parenthesis_Name => 1722, - Iir_Kind_Package_Pathname => 1726, - Iir_Kind_Absolute_Pathname => 1727, - Iir_Kind_Relative_Pathname => 1728, - Iir_Kind_Pathname_Element => 1733, - Iir_Kind_Base_Attribute => 1735, - Iir_Kind_Subtype_Attribute => 1740, - Iir_Kind_Element_Attribute => 1745, - Iir_Kind_Left_Type_Attribute => 1750, - Iir_Kind_Right_Type_Attribute => 1755, - Iir_Kind_High_Type_Attribute => 1760, - Iir_Kind_Low_Type_Attribute => 1765, - Iir_Kind_Ascending_Type_Attribute => 1770, - Iir_Kind_Image_Attribute => 1776, - Iir_Kind_Value_Attribute => 1782, - Iir_Kind_Pos_Attribute => 1788, - Iir_Kind_Val_Attribute => 1794, - Iir_Kind_Succ_Attribute => 1800, - Iir_Kind_Pred_Attribute => 1806, - Iir_Kind_Leftof_Attribute => 1812, - Iir_Kind_Rightof_Attribute => 1818, - Iir_Kind_Delayed_Attribute => 1827, - Iir_Kind_Stable_Attribute => 1836, - Iir_Kind_Quiet_Attribute => 1845, - Iir_Kind_Transaction_Attribute => 1854, - Iir_Kind_Event_Attribute => 1858, - Iir_Kind_Active_Attribute => 1862, - Iir_Kind_Last_Event_Attribute => 1866, - Iir_Kind_Last_Active_Attribute => 1870, - Iir_Kind_Last_Value_Attribute => 1874, - Iir_Kind_Driving_Attribute => 1878, - Iir_Kind_Driving_Value_Attribute => 1882, - Iir_Kind_Behavior_Attribute => 1882, - Iir_Kind_Structure_Attribute => 1882, - Iir_Kind_Simple_Name_Attribute => 1889, - Iir_Kind_Instance_Name_Attribute => 1894, - Iir_Kind_Path_Name_Attribute => 1899, - Iir_Kind_Left_Array_Attribute => 1906, - Iir_Kind_Right_Array_Attribute => 1913, - Iir_Kind_High_Array_Attribute => 1920, - Iir_Kind_Low_Array_Attribute => 1927, - Iir_Kind_Length_Array_Attribute => 1934, - Iir_Kind_Ascending_Array_Attribute => 1941, - Iir_Kind_Range_Array_Attribute => 1948, - Iir_Kind_Reverse_Range_Array_Attribute => 1955, - Iir_Kind_Attribute_Name => 1964 + Iir_Kind_Psl_Cover_Directive => 1421, + Iir_Kind_Psl_Restrict_Directive => 1432, + Iir_Kind_Block_Statement => 1446, + Iir_Kind_If_Generate_Statement => 1457, + Iir_Kind_Case_Generate_Statement => 1466, + Iir_Kind_For_Generate_Statement => 1475, + Iir_Kind_Component_Instantiation_Statement => 1486, + Iir_Kind_Psl_Default_Clock => 1490, + Iir_Kind_Simple_Simultaneous_Statement => 1497, + Iir_Kind_Generate_Statement_Body => 1508, + Iir_Kind_If_Generate_Else_Clause => 1514, + Iir_Kind_Simple_Signal_Assignment_Statement => 1524, + Iir_Kind_Conditional_Signal_Assignment_Statement => 1534, + Iir_Kind_Selected_Waveform_Assignment_Statement => 1545, + Iir_Kind_Null_Statement => 1549, + Iir_Kind_Assertion_Statement => 1556, + Iir_Kind_Report_Statement => 1562, + Iir_Kind_Wait_Statement => 1570, + Iir_Kind_Variable_Assignment_Statement => 1577, + Iir_Kind_Conditional_Variable_Assignment_Statement => 1584, + Iir_Kind_Return_Statement => 1590, + Iir_Kind_For_Loop_Statement => 1599, + Iir_Kind_While_Loop_Statement => 1608, + Iir_Kind_Next_Statement => 1615, + Iir_Kind_Exit_Statement => 1622, + Iir_Kind_Case_Statement => 1630, + Iir_Kind_Procedure_Call_Statement => 1636, + Iir_Kind_If_Statement => 1646, + Iir_Kind_Elsif => 1652, + Iir_Kind_Character_Literal => 1660, + Iir_Kind_Simple_Name => 1668, + Iir_Kind_Selected_Name => 1677, + Iir_Kind_Operator_Symbol => 1683, + Iir_Kind_Reference_Name => 1687, + Iir_Kind_External_Constant_Name => 1695, + Iir_Kind_External_Signal_Name => 1703, + Iir_Kind_External_Variable_Name => 1712, + Iir_Kind_Selected_By_All_Name => 1718, + Iir_Kind_Parenthesis_Name => 1723, + Iir_Kind_Package_Pathname => 1727, + Iir_Kind_Absolute_Pathname => 1728, + Iir_Kind_Relative_Pathname => 1729, + Iir_Kind_Pathname_Element => 1734, + Iir_Kind_Base_Attribute => 1736, + Iir_Kind_Subtype_Attribute => 1741, + Iir_Kind_Element_Attribute => 1746, + Iir_Kind_Left_Type_Attribute => 1751, + Iir_Kind_Right_Type_Attribute => 1756, + Iir_Kind_High_Type_Attribute => 1761, + Iir_Kind_Low_Type_Attribute => 1766, + Iir_Kind_Ascending_Type_Attribute => 1771, + Iir_Kind_Image_Attribute => 1777, + Iir_Kind_Value_Attribute => 1783, + Iir_Kind_Pos_Attribute => 1789, + Iir_Kind_Val_Attribute => 1795, + Iir_Kind_Succ_Attribute => 1801, + Iir_Kind_Pred_Attribute => 1807, + Iir_Kind_Leftof_Attribute => 1813, + Iir_Kind_Rightof_Attribute => 1819, + Iir_Kind_Delayed_Attribute => 1828, + Iir_Kind_Stable_Attribute => 1837, + Iir_Kind_Quiet_Attribute => 1846, + Iir_Kind_Transaction_Attribute => 1855, + Iir_Kind_Event_Attribute => 1859, + Iir_Kind_Active_Attribute => 1863, + Iir_Kind_Last_Event_Attribute => 1867, + Iir_Kind_Last_Active_Attribute => 1871, + Iir_Kind_Last_Value_Attribute => 1875, + Iir_Kind_Driving_Attribute => 1879, + Iir_Kind_Driving_Value_Attribute => 1883, + Iir_Kind_Behavior_Attribute => 1883, + Iir_Kind_Structure_Attribute => 1883, + Iir_Kind_Simple_Name_Attribute => 1890, + Iir_Kind_Instance_Name_Attribute => 1895, + Iir_Kind_Path_Name_Attribute => 1900, + Iir_Kind_Left_Array_Attribute => 1907, + Iir_Kind_Right_Array_Attribute => 1914, + Iir_Kind_High_Array_Attribute => 1921, + Iir_Kind_Low_Array_Attribute => 1928, + Iir_Kind_Length_Array_Attribute => 1935, + Iir_Kind_Ascending_Array_Attribute => 1942, + Iir_Kind_Range_Array_Attribute => 1949, + Iir_Kind_Reverse_Range_Array_Attribute => 1956, + Iir_Kind_Attribute_Name => 1965 ); function Get_Fields_First (K : Iir_Kind) return Fields_Index is @@ -9054,6 +9055,7 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Assertion_Statement | Iir_Kind_Report_Statement => return True; diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index 7c87b3df5..f706ccb86 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -2112,10 +2112,10 @@ package body Vhdl.Prints is procedure Disp_Psl_Default_Clock (Ctxt : in out Ctxt_Class; Stmt : Iir) is begin + Start_Hbox (Ctxt); if Vhdl_Std < Vhdl_08 then OOB.Put ("--psl "); end if; - Start_Hbox (Ctxt); Disp_Token (Ctxt, Tok_Psl_Default, Tok_Psl_Clock); Disp_Token (Ctxt, Tok_Is); Disp_Psl_Expression (Ctxt, Get_Psl_Boolean (Stmt)); @@ -3922,8 +3922,6 @@ package body Vhdl.Prints is Disp_Postponed (Ctxt, Stmt); Disp_Token (Ctxt, Tok_Psl_Assume); Disp_Psl_Expression (Ctxt, Get_Psl_Property (Stmt)); - Disp_Report_Expression (Ctxt, Stmt); - Disp_Severity_Expression (Ctxt, Stmt); Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); Disp_PSL_NFA (Get_PSL_NFA (Stmt)); @@ -3932,13 +3930,14 @@ package body Vhdl.Prints is procedure Disp_Psl_Cover_Directive (Ctxt : in out Ctxt_Class; Stmt : Iir) is begin + Start_Hbox (Ctxt); if Vhdl_Std < Vhdl_08 then OOB.Put ("--psl "); end if; - Start_Hbox (Ctxt); Disp_Label (Ctxt, Stmt); Disp_Token (Ctxt, Tok_Psl_Cover); Print_Sequence (Ctxt, Get_Psl_Sequence (Stmt)); + Disp_Report_Expression (Ctxt, Stmt); Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); Disp_PSL_NFA (Get_PSL_NFA (Stmt)); @@ -3947,10 +3946,10 @@ package body Vhdl.Prints is procedure Disp_Psl_Restrict_Directive (Ctxt : in out Ctxt_Class; Stmt : Iir) is begin + Start_Hbox (Ctxt); if Vhdl_Std < Vhdl_08 then OOB.Put ("--psl "); end if; - Start_Hbox (Ctxt); Disp_Label (Ctxt, Stmt); Disp_Token (Ctxt, Tok_Psl_Restrict); Print_Sequence (Ctxt, Get_Psl_Sequence (Stmt)); diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index 671c59c27..df0c1d8a1 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -736,9 +736,6 @@ package body Vhdl.Sem_Psl is is Prop : PSL_Node; begin - -- Sem report and severity expressions. - Sem_Report_Statement (Stmt); - Prop := Get_Psl_Property (Stmt); Prop := Sem_Property (Prop, True); Set_Psl_Property (Stmt, Prop); @@ -751,13 +748,10 @@ package body Vhdl.Sem_Psl is PSL.Subsets.Check_Simple (Prop); end Sem_Psl_Assume_Directive; - procedure Sem_Psl_Cover_Directive (Stmt : Iir) + procedure Sem_Psl_Sequence (Stmt : Iir) is Seq : PSL_Node; begin - -- Sem report and severity expressions. - Sem_Report_Statement (Stmt); - Seq := Get_Psl_Sequence (Stmt); Seq := Sem_Sequence (Seq); @@ -767,21 +761,18 @@ package body Vhdl.Sem_Psl is -- Check simple subset restrictions. PSL.Subsets.Check_Simple (Seq); - end Sem_Psl_Cover_Directive; + end Sem_Psl_Sequence; - procedure Sem_Psl_Restrict_Directive (Stmt : Iir) - is - Seq : PSL_Node; + procedure Sem_Psl_Cover_Directive (Stmt : Iir) is begin - Seq := Get_Psl_Sequence (Stmt); - Seq := Sem_Sequence (Seq); + Sem_Report_Expression (Stmt); - -- Properties must be clocked. - Sem_Psl_Directive_Clock (Stmt, Seq); - Set_Psl_Sequence (Stmt, Seq); + Sem_Psl_Sequence (Stmt); + end Sem_Psl_Cover_Directive; - -- Check simple subset restrictions. - PSL.Subsets.Check_Simple (Seq); + procedure Sem_Psl_Restrict_Directive (Stmt : Iir) is + begin + Sem_Psl_Sequence (Stmt); end Sem_Psl_Restrict_Directive; procedure Sem_Psl_Default_Clock (Stmt : Iir) diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb index 545a543c7..848baeeb2 100644 --- a/src/vhdl/vhdl-sem_stmts.adb +++ b/src/vhdl/vhdl-sem_stmts.adb @@ -925,8 +925,7 @@ package body Vhdl.Sem_Stmts is end if; end Sem_Return_Statement; - -- Sem for concurrent and sequential assertion statements. - procedure Sem_Report_Statement (Stmt : Iir) + procedure Sem_Report_Expression (Stmt : Iir) is Expr : Iir; begin @@ -937,6 +936,14 @@ package body Vhdl.Sem_Stmts is Expr := Eval_Expr_If_Static (Expr); Set_Report_Expression (Stmt, Expr); end if; + end Sem_Report_Expression; + + -- Sem for concurrent and sequential assertion statements. + procedure Sem_Report_Statement (Stmt : Iir) + is + Expr : Iir; + begin + Sem_Report_Expression (Stmt); Expr := Get_Severity_Expression (Stmt); if Expr /= Null_Iir then diff --git a/src/vhdl/vhdl-sem_stmts.ads b/src/vhdl/vhdl-sem_stmts.ads index 526af45ec..484727c0d 100644 --- a/src/vhdl/vhdl-sem_stmts.ads +++ b/src/vhdl/vhdl-sem_stmts.ads @@ -33,6 +33,9 @@ package Vhdl.Sem_Stmts is -- This is used by processes and subprograms analyze. procedure Sem_Sequential_Statements (Decl : Iir; Body_Parent : Iir); + -- Analyze report expression of a PSL statement. + procedure Sem_Report_Expression (Stmt : Iir); + -- Sem for concurrent and sequential assertion statements. procedure Sem_Report_Statement (Stmt : Iir); |